Anti-Fuse Memory Cell Crystal Orientation for Read Reliability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing anti-fuse memory devices with nanosheet transistors suffer from compromised reading transistor performance due to identical or similar crystal lattice directions in the active planes of the programming and reading transistors, leading to undesirable gate dielectric breakdown and reduced reliability.
Innovation Solution
Configuring the programming transistor as a fin-based transistor and the reading transistor as a nanosheet transistor with different crystal lattice directions, ensuring the active planes of both transistors are distinct, thereby improving the breakdown time and reliability of the reading transistor while maintaining decent programming performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the programming transistor and reading transistor are configured with identical or similar crystal lattice directions, then the manufacturing process is simplified, but the reading transistor performance is compromised due to gate dielectric breakdown
Solution Approach 1:
The patent applies local quality by assigning different crystal lattice directions to different transistor types within the same memory cell. Specifically, the programming transistor uses a first crystal lattice direction optimized for breakdown characteristics, while the reading transistor uses a second crystal lattice direction optimized for reliability and preventing gate dielectric breakdown. This localized differentiation resolves the contradiction by allowing each transistor to have optimal properties for its specific function.
Solution Approach 2:
The patent implements asymmetry by deliberately using different crystal lattice directions for the programming and reading transistors. This asymmetric configuration ensures that the reading transistor has superior reliability characteristics while the programming transistor maintains its breakdown functionality. The asymmetric design breaks the symmetry of using identical crystal orientations for both transistor types, thereby resolving the reliability issue.
2Reliability
If the active planes of programming and reading transistors are made distinct, then the breakdown time of the reading transistor is improved, but the device complexity increases
Solution Approach 1:
The patent applies local quality by configuring the active planes of the programming and reading transistors with different orientations. The programming transistor's active plane is oriented to facilitate controlled breakdown, while the reading transistor's active plane is oriented to maximize reliability and extend breakdown time. This localized optimization of active plane orientation resolves the contradiction between improved breakdown time and increased device complexity.
3Productivity
If nanosheet transistors are used for both programming and reading, then the device density is increased, but the reading transistor suffers from gate dielectric breakdown due to similar crystal lattice directions
Solution Approach 1:
The patent applies local quality by differentiating the crystal lattice directions of nanosheet transistors based on their functional requirements. The programming nanosheet transistor uses a first crystal lattice direction that enables effective breakdown, while the reading nanosheet transistor uses a second crystal lattice direction that prevents gate dielectric breakdown and ensures reliable operation. This localized differentiation maintains high device density while resolving the reliability issue.
Solution Approach 2:
The patent implements asymmetry by using different crystal lattice directions for the programming and reading nanosheet transistors. This asymmetric configuration allows both transistors to benefit from the high density of nanosheet architecture while ensuring the reading transistor has superior reliability characteristics through its distinct crystal orientation.
Data Source
AI summary
A semiconductor device is disclosed. The semiconductor device includes a fin-based structure formed on a substrate. The semiconductor device includes a plurality of first nanosheets, vertically spaced apart from one another, that are formed on the substrate. The semiconductor device includes a first source/drain (S/D) region electrically coupled to a first end of the fin-based structure. The semiconductor device includes a second S/D region electrically coupled to both of a second end of the fin-based structure and a first end of the plurality of first nanosheets. The semiconductor device includes a third S/D region electrically coupled to a second end of the plurality of first nanosheets. The fin-based structure has a first crystal lattice direction and the plurality of first nanosheets have a second crystal lattice direction, which is different from the first crystal lattice direction.