Anti-Fuse Memory Device Graded Impurity Profile
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving superior electrical characteristics and efficient programming of anti-fuse cells, which affect their capacity and speed, particularly in reducing parasitic currents and enhancing integration.
Innovation Solution
The semiconductor memory device incorporates a semiconductor substrate with active regions, anti-fuse gate electrodes, selection gate electrodes, and impurity regions of specific conductivity types, along with dielectric layers, to optimize the programming of anti-fuse cells by controlling voltage and reducing leakage currents through strategic impurity concentration and placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If anti-fuse cells are highly integrated to increase capacity, then storage capacity increases, but parasitic currents increase and electrical characteristics deteriorate
Solution Approach 1:
The patent applies local quality by creating a graded impurity concentration profile in the channel region. The impurity concentration varies spatially, being higher near the source/drain regions and lower in the middle section, which locally optimizes the electrical characteristics to reduce parasitic currents while maintaining high integration density.
Solution Approach 2:
The patent changes the impurity concentration parameter along the channel length to optimize device performance. By adjusting the impurity concentration gradient, the patent reduces parasitic currents and improves electrical characteristics, enabling higher integration without sacrificing performance.
2Quantity of substance
If anti-fuse gate dielectric layer thickness is reduced to increase integration density, then device density increases, but leakage currents increase and programming reliability decreases
Solution Approach 1:
The patent applies local quality by optimizing the impurity concentration distribution in the channel region adjacent to the anti-fuse gate. This local optimization compensates for the reduced dielectric thickness, maintaining programming reliability while enabling higher integration density.
Solution Approach 2:
The patent introduces the graded impurity profile as an intermediary mechanism that mediates between the conflicting requirements of thin dielectric for density and reliable programming. The impurity gradient acts as a buffer that maintains electrical control despite reduced dielectric thickness.
3Reliability
If impurity concentration in channel region is increased to reduce parasitic currents, then electrical characteristics improve, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-configuring the impurity concentration profile during the manufacturing process. The graded profile is established in advance through controlled doping steps, simplifying subsequent processing while ensuring optimal electrical characteristics are achieved.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the electrical characteristics of anti-fuse cells by reducing parasitic currents and enhancing integration, allowing for more efficient programming and data storage, thereby increasing the capacity and speed of semiconductor memory devices.
Implementation Method 1
When a high voltage is applied to an anti-fuse gate electrode, a gate dielectric layer between the anti-fuse gate electrode and a substrate experiences breakdown, and thus an ohmic contact is produced between the anti-fuse gate electrode and the substrate.
Implementation Method 2
a second impurity region in the active region between the selection gate electrode and the anti-fuse gate electrode, the second impurity region being connected to the first impurity region. The first and second impurity regions may have impurities of a second conductivity or conductivity type.
Data Source
AI summary
A semiconductor memory device includes a semiconductor substrate having an active region of a first conductivity type defined by a device isolation layer, a first impurity region in the active region, an anti-fuse gate electrode on the semiconductor substrate and extending across the first impurity region, an anti-fuse gate dielectric layer between the anti-fuse gate electrode and the first impurity region, a selection gate electrode on the semiconductor substrate and extending across the active region, a selection gate dielectric layer between the selection gate electrode and the active region, and a second impurity region in the active region between the selection gate electrode and the anti-fuse gate electrode. The first and second impurity regions have impurities of a second conductivity type. The first impurity region has an impurity concentration less than the impurity concentration of the second impurity region.