Transistor TRIZ Cases

Vertical thin film transistors use dielectric spacers to define contact periphery and increase gate length without area penalty.

An inorganic insulating layer incorporates organic-filled reinforcing holes to resolve the contradiction between insulation performance and bending resistance.

Pattern duplication transfers hard mask recess profiles to floating gates, eliminating LOCOS bird's beaks and widening the process window.

A signal switching apparatus uses a controlled surge current dissipation circuit to protect components from electrical damage.

Titanium-containing silicide layers form on doped epitaxial fins to lower contact resistance in Fin-FET devices.

A solid state imaging device aligns photoelectric conversion element positions to maintain uniform phase difference detection across the sensor array.

A semiconductor pattern layer with a diffusion prevention pattern blocks phosphorus migration in liquid crystal displays.

An asymmetrical bipolar ESD protection device manages bidirectional electrostatic discharge energy using shared collector regions and distinct emitter areas.

Oxide-to-oxide bonding aligns semiconductor layers within 40 nm error, enabling high-density connections while maintaining wiring integrity below 400°C.

Extending the high-k stack width beyond the gate region overlaps lightly doped drains, eliminating gaps that degrade threshold voltages.

Segmented contacts expand the conductive area within a metal gate layer, lowering electrical resistance while maintaining low gate leakage in CMOS transistors.

Conductive material fills trenches in the semiconductor substrate to reduce parasitic resistance while maintaining voltage blocking capability.

Shallow trench isolation delays diamond-shaped epitaxial growth on recessed fins, enabling taller structures with narrower widths to increase circuit density.

Undoped deep depletion channel structure with diffusion barrier layer reduces threshold voltage variations and improves carrier mobility.

Alternating current driving prevents ion polarization in OLEDs, maintaining light-emitting efficiency and extending device lifespan.

Asymmetric light doped drain structure suppresses abnormal edge currents to maintain display linearity and stability.

A two-gate structure controls electric fields at contact regions to reduce off-current in top gate thin film transistors.

A floating gate memory cell uses a fin-like substrate protrusion to increase channel width and current drive without expanding the planar cell area.

Gallium implantation creates an amorphous region in FinFET source/drain areas to trap dopants and lower contact resistance.

Integrating a transparent ultraviolet absorbing layer with the active layer reduces device thickness while protecting eyes from harmful outgoing light.

Optimized plasma power and gas ratios yield six-to-one etch selectivity against carbon cores, stabilizing double patterning masks.

Segmenting the base region into distinct zones with different doping levels reduces base recombination current and improves gain linearity.

Sequential read operations after write steps detect dynamic faults in scaled FinFET memory cells, improving manufacturing yield.

Widening the gate insulating layer beyond the gate electrode creates a self-service etching mask, reducing deposition steps and lowering manufacturing costs.

Switching circuits route pixel signals from distinct regions to separate analog-to-digital converters for independent processing.

Aligning the current path along the short side of the substrate minimizes horizontal resistance in flip-chip devices without adding metal layers.

Graded silicon germanium fins in a vertical fin transistor structure reduce width via selective oxidation to achieve multiple threshold voltages.

A parallel transistor device uses a wide bandgap second transistor to protect the primary silicon unit from overvoltage breakdown.

Direct substrate voltage application enables hole injection into floating gates, resolving erase efficiency bottlenecks in separated channel structures.

An insulative liner and semiconductor mandrel structure electrically isolates source-drain epitaxial regions in nanosheet transistors.

An impression cylinder integrates printing and coating processes for flexible electronic device manufacturing.

Ion implantation creates oxygen defects in oxide semiconductors, lowering contact resistance while maintaining high-speed operation performance.

Segmented dummy gate stacks guide FinFET fabrication to reduce etch loading and maintain fin flatness during metal replacement.

A hetero-BiMOS injection system uses a silicon germanium base to accelerate minority charge carriers into the floating gate.

An integrated gate structure combines stack and selection functions to improve programming efficiency without increasing memory cell size.

Stacked semiconductor layers with serially connected transistors expand memory capacity without increasing device area.

Converting the subfin base to an insulative amorphous oxide minimizes off-state leakage current while preserving front-side strain-based mobility.

Adjusting distance between doped region and isolation layer based on gate width resolves resistance variation across different transistor sizes.

Selective deposition grows a hard mask upwardly from gate electrodes, eliminating recessing and pattern-loading effects during gap-filling.

Fuse structure formed with tungsten contact plugs and connection pattern during manufacturing ensures reliable blowing and verification of fuse status.

A semiconductor fabrication method uses oxygen plasma with electron temperature at or below 1.5 eV to remove deposited material from the substrate surface.

A control device uses a parallel resistor to form a voltage divider for load monitoring.

A diffusion barrier layer prevents dopant migration into the tunnel insulating layer, maintaining layer quality during semiconductor fabrication.

Stacked semiconductor layers use local source lines and metal drain plugs to reduce electric resistance between bit lines and drain regions.

A test unit uses oxide and silicon-based semiconductor layers to detect resistive and short defects in display devices.

Replacing dielectric fill with air gaps between silicided buried bit lines reduces parasitic capacitance while maintaining high integration density.

A vertical memory cell shares a metal electrode between its transistor and capacitor to reduce footprint.

A protective coating shields insulating spacers during gate cap etching to maintain electrical separation in semiconductor structures.

Sequential metal deposition and removal steps in n-type and p-type regions reduce stress and prevent shorting in scaled gate-all-around devices.

Recessing substrate sidewalls isolates conductive structures, suppressing leakage currents and stabilizing transistor performance in ultra-thin body devices.

An oxide layer above active layers in transistors enables a wider range of driving voltages to resolve high-resolution display current constraints.

An oxygen-treated buffer layer between the bottom electrode and high-k insulator increases TDDB lifetime in scaled eDRAM devices.

Segmenting the fin with bulk material suppresses channel bottom leakage while maintaining low cost and high heat transfer advantages.

Shallow trench isolations in the silicon controlled rectifier accelerate turn-on time to mitigate fast electrostatic discharges.

A gate-bounded silicon controlled rectifier uses segmented semiconductor regions and isolation trenches to manage internal electrical parameters.

Adjustable gate width sets trigger voltage in a single ESD transistor design, eliminating multiple protection devices across different voltage ranges.

Lowering specific trench gate electrodes reduces input capacitance, preventing switching-on loss deterioration during cell shrinkage.

Deep highly doped plug reduces electric field strength and prevents overcompensation, avoiding neutral zones that cause premature breakdown.

Millisecond laser pulses heat silicon substrates above 1000°C to eliminate carbon species, resolving thermal damage risks during strained device fabrication.

Buried fin contact structures embed source and drain connections within substrate recesses, reducing short circuit risk while maintaining high packing density.

A current limiting load switch uses a dynamically generated tracking reference voltage to control power FETs and sense FETs in split-current configuration.

A semiconductor fabrication method forms a metal silicide layer on junction regions using double spacers and a self-aligned silicide process.

A hybrid dielectric fin structure combines high-k and low-k layers to provide robust isolation walls in semiconductor devices.

Parallel junction FET structures block reverse currents without increasing ON resistance, resolving reliability trade-offs in power electronics.

An asymmetric buried gate electrode reduces junction leakage while maintaining ON-state current for balanced write and refresh times.

A buried word-line trench structure with a bulged middle section increases isolation film thickness to reduce electric field interference.

A lateral diffused metal oxide semiconductor structure integrates a Schottky diode with a guard ring to reduce leakage current.

Segmented cap layers with titanium-free top regions eliminate blistering and protect ferroelectric integrity.

Source-drain electrodes cover gate insulating film end faces in oxide semiconductor thin film transistors.

Epitaxial oxide segments in fin cut spaces prevent strain relaxation, ensuring consistent carrier speeds and device performance.

A flexible substrate structure with a metal-containing layer enables laser processing of transistors.

Dummy fins inserted between active fins create uniform gaps to resolve fin structure shape inconsistencies in SRAM arrays.

A vertical MOSFET trench gate structure connects the channel p layer and source electrode via a high-concentration p+-type region.

Thinner channel oxide films in specific transistors lower RC delay, shortening output voltage settling time without increasing overall manufacturing complexity.

A silicon carbide cap epitaxial layer protects n-channel FinFET source and drain structures during manufacturing.

Segmented anode electrodes and superimposed wiring lines suppress current value variations across subpixels.

Graded impurity profiles reduce parasitic currents and enhance integration density while maintaining reliable anti-fuse cell programming.

A normally-off gallium oxide field-effect transistor structure uses high-temperature oxygen annealing to form a no-electron channel region below the gate.

Removing silicon nitride interfaces in pixel regions increases aperture ratio while maintaining electrical isolation.

A semiconductor fabrication method activates dopants via low-temperature thermal treatment.

A protective liner shields contact opening sidewalls during semiconductor processing steps.

Selective fin insulating spacers prevent short circuits in dense active regions, resolving reliability issues caused by device miniaturization.

Nested deep wells shield RF-CMOS transistors from substrate noise, reducing leakage and improving signal integrity.

An oxide semiconductor thin film comprising indium, tin, and germanium achieves high electron mobility through precise atomic ratio control.

High concentration doping in the collector region of a lateral BJT improves electrostatic discharge protection performance without increasing transistor volume.

Epitaxial growth of opposite conductivity layers within the heterojunction bipolar transistor flow enhances electrostatic discharge protection and turn-on time.

A shared control device couples target and complementary memory devices to reduce circuit footprint.

Dynamic back-plate biasing adjusts pull-down transistor strength in SRAM bitcells to optimize read stability and write speed.

Vertical stacking of insulated conductive layers increases pixel capacitance without reducing the aperture ratio in LTPS displays.

Transition cells bridge n-doped and p-doped wells in UTBOX FDSOI standard cell rows, eliminating singularity points that disrupt design rule checking.

A substrate processing apparatus integrates an ion trap unit to capture charged particles during plasma generation.

A charging device adjusts JFET gate voltage to maintain output current during the charging process.

An ESD protection circuit merges multiple pads into one shared clamp while adding a capacitor to prevent leakage currents caused by power noise.

Polymer gas etching creates uniform trench depths in dense and loose zones, resolving channel depth variations that degrade electrical performance.

Series-connected semiconductors with distinct threshold voltages generate multiple peaks and valleys in the transfer characteristic.

An oxide semiconductor transistor prevents charge leakage in static random access memory cells, maintaining data retention without continuous power supply.