Vertical thin film transistors use dielectric spacers to define contact periphery and increase gate length without area penalty.
An inorganic insulating layer incorporates organic-filled reinforcing holes to resolve the contradiction between insulation performance and bending resistance.
Pattern duplication transfers hard mask recess profiles to floating gates, eliminating LOCOS bird's beaks and widening the process window.
A signal switching apparatus uses a controlled surge current dissipation circuit to protect components from electrical damage.
Titanium-containing silicide layers form on doped epitaxial fins to lower contact resistance in Fin-FET devices.
A solid state imaging device aligns photoelectric conversion element positions to maintain uniform phase difference detection across the sensor array.
A semiconductor pattern layer with a diffusion prevention pattern blocks phosphorus migration in liquid crystal displays.
An asymmetrical bipolar ESD protection device manages bidirectional electrostatic discharge energy using shared collector regions and distinct emitter areas.
Oxide-to-oxide bonding aligns semiconductor layers within 40 nm error, enabling high-density connections while maintaining wiring integrity below 400°C.