Gate-Bounded Silicon Controlled Rectifier Latch-Up Prevention
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Solution Overview
Problem
Silicon controlled rectifiers (SCRs) used for electrostatic discharge protection in integrated circuits often experience latch-up, which can lead to damage or destruction of the circuit without warning, due to their lower holding voltage and smaller layout area, making it challenging to achieve effective electrostatic discharge protection while avoiding latch-up.
Innovation Solution
A gate-bounded silicon controlled rectifier design is implemented, incorporating a substrate with N-type and P-type well regions, semiconductor regions, and isolation trenches, along with gate structures to control the threshold voltage that triggers latch-up, thereby reducing the equivalent distance between the anode and cathode and preventing latch-up while maintaining electrostatic protection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a silicon controlled rectifier is designed with smaller layout area and lower holding voltage for electrostatic discharge protection, then the electrostatic discharge protection capability is improved, but latch-up occurs without warning causing circuit damage
Solution Approach 1:
The patent divides the SCR structure into multiple discrete semiconductor regions (first N-type, first P-type, second N-type, second P-type, and third semiconductor regions) with isolation trenches between them. This segmentation allows independent control of different functional zones, enabling the gate structure to selectively trigger or suppress latch-up in specific regions while maintaining electrostatic protection capability.
Solution Approach 2:
The gate structure acts as an intermediary element positioned between the anode and cathode regions. It controls the threshold voltage for latch-up by mediating the electrical interaction between the semiconductor regions, allowing precise control over when latch-up occurs and preventing unintended latch-up while preserving electrostatic discharge protection.
2Use of energy by moving object
If the holding voltage of the silicon controlled rectifier is reduced to afford higher electrostatic discharge energy, then the electrostatic discharge energy absorption is improved, but the latch-up threshold becomes difficult to control
Solution Approach 1:
The patent employs multiple doping concentration parameters (first doping concentration, second doping concentration, third doping concentration, fourth doping concentration) to independently control different electrical characteristics of the semiconductor regions. By adjusting these parameters, the holding voltage can be optimized for high energy absorption while the gate structure's threshold voltage is separately controlled to prevent unintended latch-up.
3Area of stationary object
If the layout area of the silicon controlled rectifier is minimized for compact integration, then the integration density is improved, but the equivalent distance between anode and cathode decreases making latch-up more likely
Solution Approach 1:
The patent introduces isolation trenches that extend vertically into the substrate, creating a three-dimensional barrier structure. This vertical dimension allows the gate structure to effectively control latch-up propagation without requiring increased horizontal spacing between anode and cathode regions, maintaining compact layout while preventing latch-up.
Data Source
AI summary
A gate-bounded silicon controlled rectifier includes a substrate, an N-type well region, a P-type well region, a first N-type semiconductor region, a first P-type semiconductor region, a second N-type semiconductor region, a second P-type semiconductor region and a third semiconductor region. The N-type well region and the P-type well region are disposed in the substrate. The first N-type semiconductor region is disposed in the N-type well region. The first P-type semiconductor region is disposed in the P-type well region. The second N-type semiconductor region is disposed in the P-type well region and located between the first N-type semiconductor region and the first P-type semiconductor region. The second P-type semiconductor region is disposed in the N-type well region and located between the first N-type semiconductor region and the first P-type semiconductor region. The third semiconductor region is located between the second N-type semiconductor region and the second P-type semiconductor region.