RF-CMOS Noise Shielding via Nested Deep Wells
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Solution Overview
Problem
In CMOS semiconductor structures, noise disturbance from the substrate affects the operation of transistors, particularly P-type transistors in N-type wells, leading to data loss and errors in logic or signal processing, especially in RF-CMOS circuits where high switching speeds are required.
Innovation Solution
The implementation of a RF-CMOS semiconductor structure with a first-conductivity-type semiconductor substrate and isolated regions, including a second-conductivity-type deep well and a first-conductivity-type deep well, forming P/N junction diodes that shield transistors from noise disturbances, utilizing shallow trench isolation and dopant implantation to enhance noise reduction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If deep N-wells are used to shield P-type transistors from substrate noise, then noise shielding is improved, but P-type transistors still experience higher noise disturbance compared to N-type transistors
Solution Approach 1:
The patent implements a nested well structure where a first-conductivity-type deep well is formed within a second-conductivity-type deep well, creating multiple concentric shielding layers. This nested configuration provides enhanced noise isolation for transistors, particularly P-type transistors in first-conductivity-type MOS regions, by establishing multiple P/N junction diodes that block substrate noise more effectively than single-layer wells.
Solution Approach 2:
The substrate is divided into first-conductivity-type MOS regions and second-conductivity-type MOS regions by isolated regions, with different well structures applied to each. First-conductivity-type MOS regions receive both first-conductivity-type deep wells and second-conductivity-type deep wells, while second-conductivity-type MOS regions receive only second-conductivity-type deep wells, creating segmented noise protection zones.
2Object-affected harmful factors
If isolation structures are added to prevent noise coupling between devices, then noise shielding is improved, but device complexity increases
Solution Approach 1:
The patent combines noise shielding functions with existing device structures by integrating deep wells into the MOS region architecture. The deep wells serve dual purposes: they provide noise shielding while also defining the boundaries and electrical characteristics of the MOS regions, eliminating the need for separate isolation structures in some cases.
Solution Approach 2:
The deep well structures serve multiple functions simultaneously: they act as noise shields, define MOS region boundaries, provide electrical isolation, and influence the electrical characteristics of transistors. This multi-functionality reduces the need for additional dedicated noise protection structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration significantly reduces noise disturbance and leak current, improving the signal-to-noise ratio and protecting transistors from substrate noise, thereby enhancing the efficiency and reliability of RF-CMOS semiconductor structures.
Implementation Method 1
The P/N junction diodes formed between the deep N-well regions and the P-type substrate prevent current flow and the deep N-wells also act as an electrical potential shield
Implementation Method 2
utilizing shallow trench isolation and dopant implantation to enhance noise reduction
Data Source
AI summary
A novel semiconductor device structure includes a first-conductivity-type semiconductor substrate, an isolated region, a first-conductivity-type MOS region, and a second-conductivity-type MOS region. A first-conductivity-type MOS transistor locates in the first-conductivity-type MOS region with a second-conductivity-type well surrounding, and a first-conductivity-type deep well surrounding the second-conductivity-type well with a second-conductivity-type deep well surrounding. In the second-conductivity-type MOS region, a second-conductivity-type MOS transistor is formed with a first-conductivity-type well surrounding. The first-conductivity-type deep well and the second-conductivity-type deep well are sufficiently reducing the noise and current leakage from other devices or from the semiconductor substrate.