Integrated Stack and Selection Gates for Flash Memory
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Solution Overview
Problem
Split gate flash memory devices have high programming efficiency and low power consumption but require additional split gate regions, increasing memory cell size and limiting integration, which hampers the enhancement of memory device performance.
Innovation Solution
A memory device with separating gates is developed, featuring stack gates and selection gates formed in the conventional stack gate regions, allowing for high programming efficiency, interference reduction, and increased data retention and cycling endurance without expanding the gate area, achieved through a specific fabrication method involving doped regions, intergate dielectric layers, and metal silicide layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If split gate flash memory is used to achieve high programming efficiency and low power consumption, then programming efficiency and power consumption are improved, but memory cell size increases due to additional split gate regions
Solution Approach 1:
The patent merges the stack gate and selection gate into a single integrated gate structure, eliminating the need for separate split gate regions. The gate structure includes a gate dielectric layer, floating gate, and control gate that serves dual functions, thereby achieving high programming efficiency without increasing memory cell area.
Solution Approach 2:
The control gate in the integrated structure performs multiple functions: it acts as both the stack gate for charge trapping and the selection gate for data access. This multi-functionality eliminates the need for additional gate regions while maintaining the programming efficiency benefits of split gate architecture.
2Productivity
If additional split gate regions are added to achieve high programming efficiency, then programming efficiency is improved, but integration is limited due to increased memory cell size
Solution Approach 1:
The patent combines multiple gate functions into a single integrated gate structure, reducing device complexity and improving integration. The unified gate structure eliminates additional split gate regions while maintaining high programming efficiency through its multi-functional design.
3Area of stationary object
If conventional stack gate structure is used to maintain small memory cell size, then integration is improved, but programming efficiency and power consumption are compromised
Solution Approach 1:
The integrated gate structure achieves multi-functionality by designing the control gate to perform both stack gate and selection gate functions. This allows the device to maintain small memory cell size like conventional stack gate while achieving high programming efficiency through the selection capability normally requiring separate split gate regions.
Data Source
AI summary
Provided is a memory device including a substrate, a source region, a drain region, a source contact, a drain contact, at least two stack gates, and at least two selection gates. The source region and the drain region are both located in the substrate. The source contact is located on the source region and the drain contact is located on the drain region. A bottom area of the drain contact is greater than a bottom area of the source contact. The stack gates are located on the substrate at two sides of the source region respectively. The selection gates are located on the substrate at two sides of the drain region respectively. A distance between the selection gates located at two sides of the drain region is greater than a distance between the stack gates located at two sides of the source region.