Fin-FET Contact Resistance Reduction via TiSiGe Silicide
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor devices shrink in size, traditional Fin-FETs face challenges with increased contact resistance due to reduced contact area, leading to degraded performance, and existing methods to reduce this resistance, such as doping and metal silicide formation, often result in Fermi level pinning and ineffective contact resistance reduction.
Innovation Solution
The method involves forming P-type and N-type fin structures with epitaxial layers doped with germanium and boron or phosphor ions, respectively, followed by the formation of titanium-containing silicide layers to reduce contact resistance through optimized annealing processes, creating TiSiGe and phosphor-doped TiSiGe metal silicide layers that lower Schottky barriers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the contact area is reduced due to device shrinkage, then the component density increases, but the contact resistance increases leading to degraded performance
Solution Approach 1:
The patent changes the material composition parameters of the contact region by forming epitaxial layers with specific doping concentrations and creating metal silicide layers with controlled stoichiometry. This transforms the electrical properties of the contact region to achieve low resistance while maintaining small device dimensions
Solution Approach 2:
The patent creates a composite contact structure consisting of multiple layers including epitaxial layers, metal silicide layers, and underlying semiconductor structures. This composite approach combines the advantages of different materials to achieve both low contact resistance and small form factor
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces contact resistance between the epitaxial layers and metal silicide contacts, enhancing the electrical performance of Fin-FET devices by minimizing Schottky barriers and improving carrier mobility.
Implementation Method 1
The first epitaxial layer is doped with P-type ions, while the first covering layer is also doped with P-type ions and contains germanium ions
Implementation Method 2
performing a first annealing process to let the titanium ions in the silicification layer diffuse into the first covering layer to form a first metal silicide layer
Implementation Method 3
performing a first annealing process to let the titanium ions in the silicification layer diffuse into the first covering layer
Implementation Method 4
The second epitaxial layer is doped with N-type ions, while the second covering layer is doped with N-type ions and contains germanium ions
Data Source
AI summary
A method for fabricating a Fin-FET device includes forming fin structures with each having a gate structure on the top in both P-type regions and N-type regions, forming a first epitaxial layer on each fin structure on both sides of the gate structure in the P-type regions, forming a P-type doped first covering layer on each first epitaxial layer, forming a second epitaxial layer on each fin structure on both sides of the gate structure in the N-type regions, forming an N-type doped second covering layer on each second epitaxial layer, and forming a titanium-containing silicification layer on the first covering layer and the second covering layer. The method further includes performing a first annealing process to let titanium ions in the silicification layer diffuse into the first covering layer to form a first metal silicide layer and into the second covering layer to form a second metal silicide layer.