Nanosheet Transistor Source-Drain Isolation via Insulative Liner and Mandrel
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Solution Overview
Problem
The challenge in integrated circuit (IC) design is to form nanosheet transistors with electrically isolated source/drain epitaxial regions across varying lateral gate-to-gate separation distances, as conventional processing techniques struggle to maintain consistency and control leakage current, especially in scaled-down structures.
Innovation Solution
The approach involves forming an insulative liner on the substrate, creating a semiconductor mandrel, and epitaxially growing source/drain epitaxial regions between nanosheet stacks, with insulator regions positioned between the mandrel and liner to ensure electrical isolation and uniform processing across different channel lengths.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional processing techniques are used to form source/drain epitaxial regions, then manufacturing simplicity is maintained, but electrical isolation and leakage current control deteriorate in scaled-down structures with varying lateral gate-to-gate separation distances
Solution Approach 1:
The source/drain formation process is segmented into two distinct stages: first forming a sacrificial source/drain region, then forming the final source/drain epitaxial region. This segmentation allows the sacrificial region to provide structural support and define the separation region during processing, while the final region provides the electrical connection, thereby achieving both electrical isolation and manufacturing feasibility
Solution Approach 2:
A sacrificial source/drain region is introduced as an intermediary element that temporarily occupies the space between nanosheet stacks during processing. This sacrificial region acts as a mediator that defines the separation region and enables subsequent epitaxial growth, but is eventually removed to achieve the desired electrical isolation and device performance
2Speed
If feature sizes of FETs are reduced to improve operating speed and density, then switching speed improves, but electrostatic control and electron mobility deteriorate
Solution Approach 1:
The invention transitions from conventional planar FET architecture to a vertically stacked nanosheet architecture. By stacking multiple nanosheets vertically between source and drain regions, the channel length is effectively extended in the vertical dimension while maintaining short lateral dimensions, thereby achieving fast switching speed with improved electrostatic control
Solution Approach 2:
Multiple nanosheets are nested vertically within a single device footprint, with each nanosheet forming a separate channel. This nesting approach allows multiple channels to be stacked in the vertical direction, increasing drive current and switching speed while maintaining compact lateral dimensions for high-density integration
3Ease of manufacture
If a single fabrication scheme is used to form differently-sized transistor structures, then manufacturing simplicity is maintained, but processing consistency deteriorates due to loading effects
Solution Approach 1:
The fabrication process incorporates local quality adjustments where the separation region geometry and epitaxial growth conditions are optimized for each specific transistor size and channel length. This allows differently-sized transistors to be formed with consistent performance characteristics despite variations in lateral dimensions, overcoming loading effects while maintaining a unified fabrication approach
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the consistent formation of electrically isolated source/drain epitaxial regions in nanosheet transistors, improving control over channel conductance and reducing leakage current, thereby enhancing the performance and scalability of IC structures.
Implementation Method 1
an insulative liner conformally positioned on the upper surface of the substrate within the separation region
Implementation Method 2
epitaxially growing a source/drain epitaxial region between the pair of nanosheet stacks, from exposed sidewalls of the pair of nanosheet stacks and the exposed upper surface of the semiconductor mandrel
Data Source
AI summary
An IC structure according to the disclosure includes: a substrate; a pair of transistor sites positioned on the substrate, wherein an upper surface of the substrate laterally between the pair of transistor sites defines a separation region; a pair of nanosheet stacks, each positioned on one of the pair of transistor sites; an insulative liner conformally positioned on the upper surface of the substrate within the separation region, and a sidewall surface of each of the pair of transistor sites; a semiconductor mandrel positioned on the insulative liner and over the separation region; a pair of insulator regions each positioned laterally between the semiconductor mandrel and the insulative liner on the sidewall surfaces of each of the pair of transistor sites; and a source/drain epitaxial region positioned over the pair of insulator regions and the semiconductor mandrel, wherein the source/drain epitaxial region laterally abuts the pair of nanosheet stacks.