Fin Transistor Bulk Channel Leakage Reduction
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Solution Overview
Problem
Conventional FinFETs suffer from current leakage at the bottom of the channel due to inadequate gate control, leading to high junction leakage and capacitance, particularly in bulk-FinFETs, which are otherwise advantageous for low cost and high heat transfer.
Innovation Solution
A fin transistor structure is developed with a bulk semiconductor material interposed between the channel region and the substrate, and an insulation material between the remaining fin portions and the substrate, eliminating the need for a punch-through stopper structure and thereby reducing current leakage without increasing junction leakage or capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a bulk-FinFET structure is used to maintain low cost and high heat transfer, then manufacturing cost and thermal performance are improved, but current leakage at the channel bottom increases
Solution Approach 1:
The fin structure is segmented into two distinct regions: a channel region with bulk semiconductor material for low cost and high heat transfer, and source/drain regions with different semiconductor material forming a heterostructure to suppress leakage. This segmentation allows each region to optimize its function while solving the overall leakage problem.
Solution Approach 2:
Different material properties are applied to different locations: the channel region uses bulk semiconductor material (e.g., Si) for cost-effectiveness and thermal performance, while the source/drain regions use a different semiconductor material (e.g., SiGe, Ge) with tailored properties to create potential barriers that suppress carrier leakage at the channel bottom.
2Loss of energy
If a punch through stopper structure with high-energy ion implantation is introduced to suppress leakage current, then current leakage is reduced, but junction leakage and junction capacitance increase
Solution Approach 1:
Instead of using high-energy ion implantation that causes broad dopant distribution and high junction doping, the invention changes the approach by forming a heterostructure through selective epitaxial growth. The leakage suppression is achieved through material composition gradients and band alignment rather than heavy doping, thereby avoiding high junction leakage and capacitance.
Solution Approach 2:
The mechanical/physical process of high-energy ion implantation is replaced with a controlled epitaxial growth process. The heterostructure is formed by depositing layers with different semiconductor materials in a controlled manner, creating potential barriers through material properties rather than through high-energy particle bombardment and subsequent diffusion.
Data Source
AI summary
There is provided a fin transistor structure and a method of fabricating the same. The fin transistor structure comprises a fin formed on a semiconductor substrate, wherein a bulk semiconductor material is formed between a portion of the fin serving as the channel region of the transistor structure and the substrate, and an insulation material is formed between remaining portions of the fin and the substrate. Thereby, it is possible to reduce the current leakage while maintaining the advantages of body-tied structures.