SiC Cap Epitaxial Layer for FinFET Alignment
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Solution Overview
Problem
In the semiconductor industry, the fabrication of fin field effect transistors (FinFETs) faces challenges in achieving precise epitaxial source and drain structures due to alignment errors during the manufacturing process, which can lead to extra junction capacitance and defect noise, especially when forming n-channel FinFETs with SiP epitaxial layers and p-channel FinFETs with SiGe epitaxial layers.
Innovation Solution
The method involves forming epitaxial source and drain structures using SiP for n-channel FinFETs and SiGe for p-channel FinFETs, with a cap epitaxial layer of SiC to prevent Ge deposition on SiC surfaces, thereby avoiding extra junction capacitance and reducing defect noise, and ensuring accurate alignment through precise epitaxial growth and protective layer management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If epitaxial source and drain structures are formed using SiP for n-channel FinFETs and SiGe for p-channel FinFETs, then device performance is improved, but alignment errors during manufacturing lead to extra junction capacitance and defect noise
Solution Approach 1:
A cap epitaxial layer of pure SiC is introduced as an intermediary between the SiGe epitaxial layer and the oxide layer. This cap layer acts as a protective barrier that prevents Ge deposition on the oxide surface, thereby eliminating the need for precise alignment between the SiGe layer and the oxide layer. The cap layer mediates the interaction between the source/drain structure and the gate oxide, resolving the alignment precision issue while maintaining the performance benefits of SiGe.
Solution Approach 2:
The cap epitaxial layer of SiC is formed in advance, before the oxide layer is deposited. This preliminary action ensures that the protective barrier is already in place to prevent Ge deposition on the oxide, eliminating the need for subsequent alignment adjustments. By performing the cap layer formation beforehand, the manufacturing process becomes more robust against alignment errors.
2Ease of manufacture
If Ge is deposited on SiC surfaces without protection, then epitaxial growth is simplified, but extra junction capacitance and defect noise are generated
Solution Approach 1:
The cap epitaxial layer of pure SiC serves as an intermediary protective layer between the SiGe epitaxial layer and the oxide layer. This cap layer prevents direct contact between Ge and the oxide surface, thereby eliminating the harmful effects of Ge deposition on the oxide (extra junction capacitance and defect noise) while allowing the epitaxial growth process to remain relatively simple.
3Manufacturing precision
If alignment precision is improved to prevent Ge deposition on oxide, then defect noise is reduced, but manufacturing complexity increases
Solution Approach 1:
By introducing the cap epitaxial layer as a mediator, the patent reduces the need for high-precision alignment between the SiGe layer and the oxide layer. The cap layer absorbs the alignment tolerance requirements, thereby reducing manufacturing complexity while still preventing Ge deposition on the oxide surface and eliminating defect noise.
Solution Approach 2:
The cap layer is formed in advance as a preliminary protective barrier. This preliminary action simplifies subsequent manufacturing steps by eliminating the need for precise alignment control during oxide deposition, thereby reducing overall manufacturing complexity while maintaining high alignment accuracy where needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces defect noise and extra junction capacitance, allowing for more precise control over FinFET structures and improved device performance by ensuring accurate epitaxial growth and minimizing misalignment errors during the manufacturing process.
Implementation Method 1
a cap epitaxial layer of SiC to prevent Ge deposition on SiC surfaces
Data Source
AI summary
In a method of manufacturing a semiconductor device, a first fin structure for an n-channel fin field effect transistor (FinFET) is formed over a substrate. An isolation insulating layer is formed over the substrate such that an upper portion of the first fin structure protrudes from the isolation insulating layer. A gate structure is formed over a part of the upper portion of the first fin structure. A first source/drain (S/D) epitaxial layer is formed over the first fin structure not covered by the gate structure. A cap epitaxial layer is formed over the first S/D epitaxial layer. The first S/D epitaxial layer includes SiP, and the cap epitaxial layer includes SiC with a carbon concentration is in a range from 0.5 atomic % to 5 atomic %.