SRAM Bitcell Back-Plate Biasing for Vmin and Yield
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Solution Overview
Problem
Static random access memory (SRAM) bitcells fabricated on a silicon-on-insulator (SOI) substrate face challenges in achieving improved minimum operating voltage (Vmin) and yield, as they struggle with power consumption, data retention, and reliability at lower supply voltages due to limitations in transistor biasing and isolation.
Innovation Solution
The SRAM bitcell structures incorporate a deep n-well layer, p-well regions, doped back-plate regions, buried oxide layers, and polysilicon gate conductors, along with shallow and deep trench isolation regions, to facilitate dynamic biasing of transistors through contact to back-plate regions, optimizing the biasing of pull-down and pull-up transistors for improved read and write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If SRAM bitcells are designed to operate at lower power supplies to reduce power dissipation, then power consumption is reduced, but the minimum operating voltage (Vmin) and yield deteriorate
Solution Approach 1:
The patent implements dynamic biasing of pull-down transistors where the back-plate voltage is adjusted based on operation mode (read, write, or standby). During read operations, the back-plate is biased to enhance pull-down strength for better read stability. During write operations, the bias is adjusted to facilitate writeability. This dynamic adjustment allows the bitcell to maintain high yield and reliability at lower supply voltages while still achieving reduced power dissipation.
Solution Approach 2:
The patent changes the electrical parameters (voltage bias) of the pull-down transistor back-plate to optimize performance. By varying the back-plate voltage parameter, the effective threshold voltage and drive strength of pull-down transistors are adjusted, enabling the bitcell to operate reliably at lower supply voltages without sacrificing yield.
2Loss of energy
If SRAM bitcells operate at minimum operating voltage (Vmin) to reduce power consumption, then power dissipation is reduced, but data retention and reliability worsen
Solution Approach 1:
The patent employs dynamic biasing where the back-plate voltage of pull-down transistors is adjusted according to the operational state. During standby mode, the bias is configured to maximize data retention by maintaining strong pull-down capability. During active read/write operations, the bias is optimized for speed and writeability. This dynamic adaptation enables reliable data retention at minimum operating voltage.
Solution Approach 2:
The patent prepares the transistor biasing conditions in advance for different operation modes. The back-plate biasing is pre-configured to ensure optimal data retention characteristics before read/write operations occur, allowing the bitcell to maintain stability even at reduced supply voltages.
3Device complexity
If conventional SRAM bitcell structures are used without dynamic biasing, then device complexity is reduced, but minimum operating voltage (Vmin) and yield worsen
Solution Approach 1:
The patent makes the back-plate structure multi-functional by using it for both mechanical support and electrical biasing control. The same back-plate region serves as the substrate for the pull-down transistor while also providing a controllable voltage bias terminal. This universal usage achieves dynamic performance optimization without significantly increasing device complexity.
Solution Approach 2:
The pull-down transistor's back-plate serves its own biasing needs through the controllable back-plate voltage terminal. The structure is self-sufficient in that the back-plate region inherently provides both structural support and electrical bias control, eliminating the need for separate biasing circuits and maintaining simplicity while improving yield.
Data Source
AI summary
Static random access memory (SRAM) bitcell structures with improved minimum operation voltage (Vmin) and yield are provided. The structures may include a silicon substrate, a deep n-well (DNW) layer, p-well (PW) regions, doped back-plate (BP) regions, a buried oxide (BOX) layer, and/or active regions formed on the BOX layer and over portions of the BP regions. At least one BP region may extend below at least one shallow trench isolation (STI) region, at least one contact to back plate (CBP), at least one active region and at least one PC construct overlapping the at least one active region forming a channel of at least one of a first pull-down (PD1) transistor and a second pull-down (PD2) transistor. The at least one CBP facilitates biasing at least one of the PD1 and PD2 transistors during at least one of a read, write or standby operation of the structures.