FinFET Dummy Gate Stack Segmentation for Etch Loading Reduction
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Solution Overview
Problem
The challenge in semiconductor manufacturing lies in forming reliable three-dimensional FinFET devices as feature sizes decrease, making fabrication processes increasingly difficult due to the complexity of forming and isolating fin structures and gate stacks.
Innovation Solution
A method involving the formation of fin structures over a semiconductor substrate, followed by the deposition of isolation structures, gate electrode layers, and dummy gate stacks, with subsequent spacer formation and source/drain feature creation, and finally replacing the dummy gate stacks with metal gate stacks to enhance device reliability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If three-dimensional FinFET structures are formed to overcome scaling challenges, then device performance is improved, but fabrication process complexity increases
Solution Approach 1:
The gate structure is segmented into multiple components: a gate dielectric layer, a work function layer, and a conductive filling layer. This segmentation allows each layer to be optimized independently for its specific function, improving overall device performance while enabling systematic fabrication processes
Solution Approach 2:
A dummy gate stack is formed over the fin structure before source/drain features are created. This preliminary gate structure serves as a placeholder that guides subsequent processing steps, including spacer formation and etch operations, thereby simplifying the overall fabrication sequence
2Ease of manufacture
If dummy gate stacks are formed over fin structures, then fabrication processability is improved, but etch loading increases
Solution Approach 1:
The dummy gate stack is positioned specifically over the fin structure where it is needed for process guidance, while other areas are left without dummy structures. This localized placement provides fabrication benefits only where required, minimizing unnecessary etch loading in other regions
Solution Approach 2:
The dummy gate stack partially covers the fin structure rather than completely enveloping it. This partial coverage provides sufficient process guidance during fabrication while reducing the total material volume that would contribute to etch loading compared to a complete coverage approach
3Reliability
If gate stacks are formed to control channels from multiple sides, then short channel effect is reduced, but structural reliability becomes challenging
Solution Approach 1:
The gate stack employs a composite structure with multiple functional layers: a gate dielectric layer for electrical isolation, a work function layer for proper band alignment, and a conductive filling layer for gate electrode formation. This composite approach enables effective multi-sided channel control while maintaining structural integrity through carefully selected material properties
Solution Approach 2:
The gate structure is nested within a protective cavity formed in the isolation structure. The gate stack (dielectric layer, work function layer, and conductive layer) is sequentially deposited and formed within this pre-defined space, providing mechanical support and structural reliability while enabling the complex multi-layer gate configuration
Data Source
AI summary
Structures and formation methods of a semiconductor device are provided. The method includes forming a first fin structure and a second fin structure over a substrate, and forming first, second and third dummy gate stacks over the substrate. The first dummy gate stack and the second dummy gate stack partially cover the first fin structure and the second fin structure respectively. The third dummy gate stack is between the first dummy gate stack and the second dummy gate stack. The method also includes partially removing the third dummy gate stack such that a semiconductor layer of the third dummy gate stack remains over the substrate, forming a protection layer over the semiconductor layer, and replacing the first dummy gate stack and second dummy gate stack with a first gate stack and a second gate stack, respectively.