Semiconductor Device Substrate Sidewall Recess for Leakage Suppression
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Solution Overview
Problem
Transistors formed using conventional semiconductor-on-insulator substrates with ultra-thin body and buried oxide exhibit unstable performance due to short-circuit issues caused by the thinness of the semiconductor and insulating layers, leading to leakage currents and reduced integration density.
Innovation Solution
A method involving the formation of first and second openings in the semiconductor layer, with spacers protecting the sidewalls during etching, allowing for a shorter distance between substrate sidewalls in the second openings, which prevents short-circuits by recessing the substrate sidewalls, thereby ensuring stable transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the semiconductor layer and insulating layer are made ultra-thin to reduce transistor size and suppress short channel effect, then the transistor size is reduced and short channel effect is suppressed, but the transistor performance becomes unstable due to short-circuit issues
Solution Approach 1:
The method performs preliminary etching of the substrate sidewalls before forming the gate structure. By recessing the substrate sidewalls in advance through selective etching, the patent prevents potential short-circuits between conductive structures and the substrate, thereby ensuring stable transistor performance while maintaining ultra-thin layer dimensions
Solution Approach 2:
The patent introduces an intermediate etching step that acts as a mediator between the ultra-thin layer formation and the final device assembly. This intermediate step recesses the substrate sidewalls, creating a buffer zone that prevents direct contact between conductive structures and the substrate, thus resolving the short-circuit issue
2Productivity
If the gate dimension is reduced to increase component density and integration density, then the component density and integration density increase, but short channel effect occurs causing leakage current
Solution Approach 1:
The patent segments the transistor structure into distinct regions with the substrate sidewalls recessed away from the channel region. This segmentation creates physical separation between the conductive structures and the substrate, preventing leakage current paths while allowing continued scaling of the gate dimension for higher integration density
3Length of moving object
If the semiconductor layer thickness is reduced to form ultra-thin body, then the transistor size is reduced and short channel effect is suppressed, but short-circuits occur between conductive structures and substrate
Solution Approach 1:
The method performs preliminary etching of the substrate sidewalls before forming the gate structure. By recessing the substrate sidewalls in advance through selective etching, the patent prevents potential short-circuits between conductive structures and the substrate, thereby ensuring stable transistor performance while maintaining ultra-thin layer dimensions
Solution Approach 2:
The patent addresses the short-circuit problem by moving in a different dimensional direction - instead of increasing the vertical distance between conductive structures and substrate, it recesses the substrate sidewalls horizontally away from the channel region, creating lateral separation that prevents short-circuits while maintaining ultra-thin layer thickness
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach stabilizes transistor performance by preventing short-circuits and improving yield, as the conductive structures are electrically isolated from the substrate, effectively suppressing leakage currents and enhancing integration density.
Implementation Method 1
The insulating layer and the substrate are etched through the bottom surface of each first opening employing the semiconductor layer and the spacers as an etch mask to form a plurality of second openings through the insulating layer and into the substrate
Implementation Method 2
Spacers are formed on sidewall surfaces of each first opening in the semiconductor layer. The insulating layer and the substrate are etched through the bottom surface of each first opening employing the semiconductor layer and the spacers as an etch mask
Implementation Method 3
the conductive structures are electrically isolated from the substrate, effectively suppressing leakage currents
Data Source
AI summary
The present disclosure provides semiconductor devices and fabrication methods thereof. A stacked substrate includes an insulating layer between a substrate and a semiconductor layer. First openings are formed in the semiconductor layer to define a first distance between adjacent sidewalls of adjacent first openings. Spacers are formed on sidewall surfaces of each first opening. Second openings corresponding to the first openings are formed through the insulating layer and into the substrate. The sidewall surfaces of the substrate in the second openings are etched to define a second distance between adjacent substrate sidewalls of adjacent etched second openings. The second distance is shorter than the first distance. An isolation layer is formed in the first and second openings. Conductive structures are formed on the semiconductor layer on both sides of a gate structure formed on the semiconductor layer. The conductive structures penetrate through the isolation layer and into the substrate.