3D Semiconductor Stacking via Oxide-to-Oxide Bonding
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Solution Overview
Problem
Current 3D semiconductor chip stacking technologies face challenges in achieving high-density connections between layers due to misalignment issues and temperature limitations, which degrade transistor and wiring performance, and existing methods struggle to construct transistors above wiring layers without damaging them.
Innovation Solution
The development of a method for constructing 3D semiconductor devices with single crystal transistors and oxide-to-oxide bonding, allowing for high-density connectivity and alignment with less than 40 nm error, using techniques such as layer transfer and ion-cut to form horizontally-oriented transistors and resistance-based memory elements with side gates, enabling sub-400°C processing temperatures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistors are constructed at high temperatures (>700°C) to improve transistor performance, then transistor density and performance improve, but wiring layers are damaged due to exposure to temperatures higher than 400°C
Solution Approach 1:
The patent divides the semiconductor structure into separate temperature zones: a first semiconductor layer processed at high temperature (>700°C) for transistor formation, and a second semiconductor layer processed at low temperature (<400°C) for wiring formation. This segmentation allows each layer to be optimized for its specific temperature requirements without interfering with the other layer's integrity.
Solution Approach 2:
The patent transitions from planar 2D integration to 3D vertical stacking, placing the high-temperature transistor layer and low-temperature wiring layer in different vertical dimensions. This dimensional separation enables simultaneous high-temperature processing for transistors without damaging the wiring layer, as the wiring layer is positioned in a protected vertical zone.
2Speed
If 3D stacking is implemented to reduce wire lengths and improve performance, then wiring delay decreases, but alignment precision deteriorates due to misalignment issues between layers
Solution Approach 1:
The patent performs preliminary alignment mark formation on the first semiconductor layer before stacking. These alignment marks are created in advance to guide the precise positioning of the second semiconductor layer during the stacking process, ensuring accurate alignment despite the complexity of 3D integration.
Solution Approach 2:
The patent replaces traditional mechanical alignment methods with optical alignment techniques using alignment marks and lithographic patterning. This substitution enables sub-40nm alignment precision by using light-based methods rather than mechanical positioning, significantly improving alignment accuracy in 3D stacked structures.
3Adaptability or versatility
If conventional 3D stacking methods are used to connect layers, then layer connectivity is achieved, but connection density is limited due to large contact sizes and low number of connections
Solution Approach 1:
The patent implements a nested structure where through-silicon vias (TSVs) are formed within the semiconductor layers, allowing multiple interconnection levels to be nested vertically. This nesting enables high-density connections by stacking multiple interconnect layers, achieving billions of connections between layers rather than the limited 10,000 connections in conventional methods.
Solution Approach 2:
The patent changes the contact size parameter from large conventional dimensions to sub-40nm dimensions through advanced lithographic techniques. This parameter change enables significantly higher connection density by reducing the footprint of each contact, allowing many more connections to be packed into the same area.
4Ease of manufacture
If misalignment tolerance is increased to accommodate manufacturing variations, then ease of manufacture improves, but alignment precision deteriorates beyond 40nm error
Solution Approach 1:
The patent implements a feedback mechanism where alignment marks are used to measure actual alignment deviations, and this information feeds back into the positioning process for subsequent layers. This closed-loop approach allows the system to compensate for manufacturing variations while maintaining sub-40nm alignment precision, rather than requiring excessive tolerance that would degrade accuracy.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the construction of 3D semiconductor devices with high-density connections and improved transistor performance by allowing for precise alignment and sub-400°C processing, overcoming the limitations of existing technologies in 3D chip stacking.
Implementation Method 1
using techniques such as layer transfer and ion-cut to form horizontally-oriented transistors
Implementation Method 2
The development of a method for constructing 3D semiconductor devices with single crystal transistors and oxide-to-oxide bonding, allowing for high-density connectivity and alignment with less than 40 nm error
Data Source
AI summary
A method for producing a 3D semiconductor device, the method comprising: providing a first level, said first level comprising a first single crystal layer; forming first alignment marks and control circuits in and/or on said first level, wherein said control circuits comprise first single crystal transistors, and wherein said control circuits comprise at least two interconnection metal layers; forming at least one second level disposed on top of said control circuits; performing a first etch step into said second level; and performing additional processing steps to form a plurality of first memory cells within said second level, wherein each of said memory cells comprise at least one second transistors, and wherein said additional processing steps comprise depositing a gate electrode for said second transistors.