Parallel MOSFET Junction FET Reverse Current Blocking
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Solution Overview
Problem
Conventional semiconductor devices face issues with high ON resistance in p-channel MOSFETs, increased costs due to larger chip areas, and high leak currents when using Schottky barriers or serially connected MOSFETs to prevent reverse connection damage, which are inefficient in blocking reverse current flows.
Innovation Solution
A semiconductor device comprising an enhancement mode MOSFET and a junction FET with a parallel pn region structure, where the junction FET has a lower resistance than conventional devices, and the enhancement mode MOSFET does not use Schottky connections, allowing for effective blocking of reverse current flows by applying a predetermined voltage to the gate electrode of the junction FET.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If p-channel MOSFETs are used to prevent reverse connection damage, then reverse current blocking capability is improved, but ON resistance increases significantly
Solution Approach 1:
The patent combines an n-channel MOSFET and a p-channel MOSFET in a parallel configuration where both transistors share common source and drain regions. This merging allows the device to leverage the low ON resistance of the n-channel MOSFET during normal operation while maintaining the reverse current blocking capability of the p-channel MOSFET, thus resolving the contradiction between low resistance and reverse protection.
Solution Approach 2:
The parallel-connected MOSFET structure serves multiple functions: the n-channel MOSFET provides low-resistance current conduction during normal operation, while the p-channel MOSFET provides reverse voltage blocking. This multi-functionality eliminates the need for separate protection circuits and achieves both low ON resistance and reliable reverse connection prevention within a single integrated device structure.
2Reliability
If Schottky barriers are used for reverse connection prevention, then reverse current blocking is improved, but leak currents increase
Solution Approach 1:
Instead of using Schottky barriers which generate significant leak currents, the patent employs junction diodes formed by p-n junctions in the parallel MOSFET structure. These junction diodes provide reliable reverse connection prevention with minimal leak currents, effectively replacing the problematic Schottky barrier approach with a more suitable semiconductor junction-based solution.
3Reliability
If MOSFETs are connected in series to prevent reverse connection, then reverse current blocking is improved, but device complexity increases
Solution Approach 1:
The patent merges the reverse protection function into the main current conduction path by using parallel-connected MOSFETs with shared source and drain regions. This configuration achieves reverse current blocking without requiring separate series-connected protection devices, thereby preventing the increase in device complexity that would result from series connections while maintaining reliable reverse protection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces ON resistance and suppresses leak currents, effectively preventing damage from reverse current flows while maintaining low resistance, thus enhancing the reliability and efficiency of the semiconductor device.
Implementation Method 1
A semiconductor device comprises an enhancement mode MOSFET and a junction FET with a parallel pn region structure, where the junction FET has a lower resistance than conventional devices, and the enhancement mode MOSFET does not use Schottky connections, allowing for effective blocking of reverse current flows by applying a predetermined voltage to the gate electrode of the junction FET.
Data Source
AI summary
A semiconductor device includes an enhancement mode MOSFET and a junction FET. The MOSFET has a first semiconductor substrate of a first conductivity type, a first first-semiconductor-layer of the first conductivity type, first second-semiconductor-regions of a second conductivity type, first first-semiconductor-regions of the first conductivity type, first gate insulating films, first gate electrodes, a first first-electrode, and a first second-electrode. The FET has a second semiconductor substrate of the first conductivity type, a second first-semiconductor-layer of the first conductivity type, second first-semiconductor-regions of the first conductivity type, a second second-semiconductor-layer of the second conductivity type, second gate electrodes, a second first-electrode, and a second second-electrode. The first second-electrode and the second second-electrode are connected electrically.