Multilevel Semiconductor Devices With Local Source Lines
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In multilevel semiconductor devices, the increased electric resistance between bit lines and drain regions due to complex line structures and the difficulty in applying self-aligned source techniques hinder the improvement of integration density and operating speed, particularly in NOR flash memory devices.
Innovation Solution
The semiconductor devices feature a multilevel structure with stacked semiconductor layers, local source line structures, and drain plugs made of metal materials that connect source and drain regions directly to bit lines without intervening select transistors, reducing electric resistance and enabling efficient integration and operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistors are arranged in a multilevel structure to increase integration density, then integration density is improved, but electric resistance of connecting lines increases
Solution Approach 1:
The patent transitions from planar transistor arrangement to three-dimensional multilevel stacking, adding vertical dimension to increase integration density. Multiple semiconductor layers are stacked with transistors formed on each layer, connected through vertical plug structures, thereby achieving higher density without compromising electrical performance through optimized inter-layer connections.
Solution Approach 2:
The patent introduces select transistor structures as intermediary elements that facilitate low-resistance electrical connections between bit lines and drain regions across multiple layers. These select transistors act as controlled pathways, reducing the overall resistance in the complex multilevel interconnect structure.
2Quantity of substance
If complex line structures are used to connect transistors in multilevel arrangement, then integration density is improved, but operating speed deteriorates
Solution Approach 1:
The patent optimizes electrical parameters by using metal materials with superior conductivity for plug structures and interconnect lines. The selective use of low-resistance materials and optimized geometrical parameters of connecting structures reduces RC delays, thereby maintaining high operating speed despite the complex multilevel architecture.
3Ease of manufacture
If device isolation layer patterns have identical thickness to semiconductor layers, then manufacturing is simplified, but self-aligned source technique cannot be applied
Solution Approach 1:
The patent implements varying thicknesses of device isolation layer patterns at different locations. Specifically, the isolation layer thickness is designed to be greater than semiconductor layer thickness in certain regions, creating local variations that enable proper exposure of semiconductor substrate for self-aligned source implantation while maintaining overall manufacturing feasibility.
Data Source
AI summary
Semiconductor devices including a plurality of semiconductor layers. A plurality of transistors are on each of the semiconductor layers. The transistors include gate lines and have source regions and drain regions formed between the gate lines in the respective semiconductor layer including the transistors. The semiconductor devices further include a plurality of local source line structures. Each of the local source line structures is positioned on a corresponding one of the semiconductor layers and connects a plurality of the source regions formed on the corresponding one of the semiconductor layers. Methods of forming the semiconductor devices are also provided.