Integrated Schottky Diode Guard Ring LDMOS Process
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Incorporating Schottky diodes with high-voltage capability into integrated circuits, particularly within CMOS devices, is challenging due to increased manufacturing costs and complexity, as it requires additional masking and metal deposition steps, and existing methods struggle to effectively manage high electric fields.
Innovation Solution
A Schottky diode design utilizing a lateral diffused metal-oxide semiconductor (LDMOS) process with an epitaxial layer, buried layer, and strategically positioned Pdrift regions, along with Schottky and ohmic contacts, to create a high-voltage capable diode that reduces leakage and electric field strength through a depletion region, allowing for concurrent integration with LDMOS transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If Schottky diodes are incorporated into integrated circuit manufacturing process, then performance is improved (smaller forward bias voltage drop, lower power consumption), but manufacturing cost and complexity increase (additional masking steps and metal deposition steps)
Solution Approach 1:
The patent merges the Schottky diode manufacturing process with the existing CMOS fabrication process by forming the Schottky contact during the same metal deposition step used for other interconnect layers. This integration eliminates separate masking and deposition steps that would otherwise be required, thereby reducing manufacturing complexity while maintaining the low power consumption benefits of Schottky diodes
Solution Approach 2:
The metal layer deposited for standard CMOS interconnect purposes is made to serve dual functions: as both the interconnect metal and as the Schottky contact anode. This multi-functionality approach allows the same manufacturing step to create both standard circuit connections and Schottky barrier diodes, reducing overall process complexity
2Loss of energy
If Schottky diodes are incorporated into integrated circuit manufacturing process, then performance is improved (smaller forward bias voltage drop), but manufacturing cost increases (additional masking steps and metal deposition steps)
Solution Approach 1:
The patent combines the Schottky contact formation with existing CMOS metal deposition processes, eliminating the need for separate manufacturing steps. By utilizing the same metal layer and deposition equipment already required for standard interconnects, the patent avoids additional material costs and processing expenses while maintaining the energy efficiency advantages of Schottky diodes
3Reliability
If high-voltage Schottky diodes are manufactured, then voltage capability is improved, but manufacturing difficulty increases (difficult to manufacture into CMOS devices)
Solution Approach 1:
The patent applies local quality by creating a specialized drift region with controlled doping profiles specifically in the high-voltage Schottky diode areas, while leaving the rest of the CMOS circuitry with standard doping characteristics. This localized modification allows high-voltage operation in specific regions without compromising the overall CMOS fabrication process or requiring changes to low-voltage circuit areas
Solution Approach 2:
The patent utilizes parameter changes by adjusting doping concentrations, junction depths, and depletion region dimensions during standard CMOS processing steps to achieve high-voltage capability. By modifying these parameters within existing process windows, the patent enables high-voltage Schottky diode fabrication using standard CMOS equipment and materials
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of high-voltage Schottky diodes within CMOS devices with reduced manufacturing costs and improved performance by minimizing leakage and electric field strength, thus enhancing the operational efficiency of integrated circuits.
Implementation Method 1
strategically positioned Pdrift regions, along with Schottky and ohmic contacts, to create a high-voltage capable diode that reduces leakage and electric field strength through a depletion region
Data Source
AI summary
Described examples include an integrated circuit having a semiconductor substrate having an epitaxial layer located thereon, the epitaxial layer having a surface. The integrated circuit also has a buried layer formed in the semiconductor substrate, the epitaxial layer located between the buried layer and the surface. The integrated circuit also has a Schottky contact and an ohmic contact formed on the surface. The integrated circuit also has a Pdrift region in the epitaxial layer located between the ohmic contact and the Schottky contact.