Shared Control Device for Differential Memory Circuit Footprint
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Solution Overview
Problem
Memory circuits using differential sensing require larger cell sizes due to the need for both target and complementary devices, leading to increased silicon area consumption and longer write times compared to single-ended sensing schemes.
Innovation Solution
A memory circuit with a shared control device that allows concurrent access and writing to both target and complementary memory devices using a small footprint, where the upper electrode of one device is connected to the lower electrode of the other, enabling opposite potential differences for data states, thus reducing the overall size and write time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If differential sensing is used in memory circuits, then measurement precision is improved, but area of stationary object increases
Solution Approach 1:
The patent merges the control functions for target and complementary memory devices into a single shared control device. The shared control device has a first terminal coupled to a source-line, a second terminal coupled to a word-line, and a third terminal that concurrently controls both the target memory device (via first upper electrode) and complementary memory device (via second lower electrode), thereby reducing the overall circuit footprint while maintaining differential sensing capability
Solution Approach 2:
The shared control device performs multiple functions: it controls the target memory device through its first upper electrode and simultaneously controls the complementary memory device through its second lower electrode. This multi-functional approach allows a single device to replace what would traditionally require separate control devices for each memory cell, reducing silicon area consumption
2Measurement precision
If differential sensing is used in memory circuits, then measurement precision is improved, but duration of action of stationary object increases
Solution Approach 1:
The patent merges the control functions for target and complementary memory devices into a single shared control device. The shared control device has a first terminal coupled to a source-line, a second terminal coupled to a word-line, and a third terminal that concurrently controls both the target memory device (via first upper electrode) and complementary memory device (via second lower electrode), thereby reducing the overall circuit footprint while maintaining differential sensing capability
Solution Approach 2:
The shared control device enables concurrent writing operations to both target and complementary memory devices through its third terminal. By applying appropriate voltages to the first upper electrode and second lower electrode simultaneously, the system performs differential writing in a continuous manner, reducing the overall write time compared to sequential operations
3Area of stationary object
If shared control device is used to access both target and complementary memory devices, then area of stationary object is reduced, but device complexity increases
Solution Approach 1:
The shared control device is segmented into distinct terminals with specific functions: a first terminal for source-line connection, a second terminal for word-line connection, and a third terminal for concurrent control of both memory devices. This segmentation allows the complex control function to be organized into manageable, functionally-separated components, making the design more implementable despite the increased functionality
Data Source
AI summary
The present disclosure, in some embodiments, relates to a method of forming an integrated chip. The method may include forming a control device within a substrate. A first plurality of interconnect layers are formed within a first inter-level dielectric (ILD) structure over the substrate. A first memory device and a second memory device are formed over the first ILD structure. A second plurality of interconnect layers are formed within a second ILD structure over the first ILD structure. The first plurality of interconnect layers and the second plurality of interconnect layers couple the first memory device and the second memory device to the control device.


