LTPS Array Substrate Storage Capacitance via Vertical Stacking

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Solution Overview

Problem

Existing LTPS TFT LCDs face challenges in increasing pixel capacitance without reducing the aperture ratio, as the metal layer enlargement does not lead to significant increments in pixel capacitance, and current pixel structures are inefficient in integrating driving circuits on glass substrates.

Innovation Solution

A low temperature poly-silicon (LTPS) array substrate design featuring a stack structure with insulated conductive layers, a polysilicon layer, and a source-drain metal layer, where the storage capacitance is increased by forming a large area storage capacitance below a black matrix, and the common electrode is positioned under a conductive trench to prevent current leakage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the metal layer is enlarged to increase pixel capacitance, then the pixel capacitance increases, but the aperture ratio decreases

Engineering Contradiction:

Improvepixel capacitanceVSAvoidaperture ratio

Core Design Contradiction:

Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent introduces a vertical stacking dimension by placing the first and second conductive layers at different heights (stacked structure) to form storage capacitance. This three-dimensional arrangement allows the storage capacitance to be formed below the black matrix rather than expanding the metal layer area in the planar dimension, thereby increasing pixel capacitance without reducing the aperture ratio.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent embeds the storage capacitance structure (first and second conductive layers) within the space below the black matrix and pixel electrode. By nesting the capacitance-forming elements in the vertical space beneath existing structures, the design increases pixel capacitance without occupying additional lateral area that would reduce the aperture ratio.

Inventive Principle:

Principle #7Nested doll (Nesting)

2Quantity of substance

If the metal layer area is increased to improve pixel capacitance, then pixel capacitance increases, but the manufacturing complexity increases

Engineering Contradiction:

Improvepixel capacitanceVSAvoidmanufacturing complexity

Core Design Contradiction:

Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent divides the capacitance structure into separate first and second conductive layers stacked vertically, with the first conductive layer forming the storage capacitance and the second conductive layer serving as the pixel electrode. This segmentation allows each layer to be optimized independently and simplifies the manufacturing process compared to enlarging a single metal layer.

Inventive Principle:

Principle #1Segmentation

Data Source

PatentUS9640559B2Low temperature poly-silicon array substrate and forming method thereof

Publication Date: 2017.05.02 XIAMEN TIANMA MICRO ELECTRONICS

AI summary

A low temperature poly-silicon (LTPS) array substrate is disclosed. The array substrate includes a first substrate and a stack structure on the first substrate, where the stack structure includes a first conductive layer, and a second conductive layer. The first and second conductive layers are insulated from each other. The array substrate also includes a polysilicon layer above the first and second conductive layers, an interlayer insulating layer above the polysilicon layer, and a source-drain metal layer on the interlayer insulating layer. The source-drain metal layer includes a source and a drain, the source and the drain are electrically connected with the polysilicon layer through a first via, and one of the source and the drain is electrically connected with the first conductive layer through a second via.