Vertical Non-Volatile Memory Device with Direct Substrate Erase
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Solution Overview
Problem
Current three-dimensional non-volatile memory devices face challenges in integration intensity and efficient erase operations, with structures like PBiCS struggling to perform conventional erase methods due to channel separation from the substrate and TCAT having high source line resistance from ion implantation processes.
Innovation Solution
A non-volatile memory device with vertically stacked memory cells featuring direct connections between active regions and channels, allowing for efficient erase operations by applying an erase voltage directly to the semiconductor substrate, reducing line resistance through metal source and bit lines, and using ion implantation regions for program and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a channel is separated from a substrate body in the PBiCS structure, then integration intensity is improved, but erase operation efficiency deteriorates
Solution Approach 1:
The device is divided into multiple stacked layers with bit lines and source lines disposed on upper and lower parts of the stacked memory cell, allowing independent optimization of each segment for both integration density and erase operation performance
Solution Approach 2:
A metal source line is introduced as an intermediary component to reduce resistance and improve hole injection efficiency during erase operations, while maintaining the separated channel structure for high integration intensity
2Productivity
If holes are generated by applying high voltage to the selected gate and generating GIDL current, then erase operation can occur in separated channel structure, but control difficulty increases and efficiency decreases
Solution Approach 1:
Instead of applying high voltage to the gate to generate GIDL current, the invention applies high voltage directly to the substrate body to generate holes that are injected into the floating gate, inverting the voltage application approach to achieve better control and efficiency
Solution Approach 2:
The voltage application parameters are changed from gate-centric (GIDL) to substrate-centric, allowing precise control of hole generation and injection timing, thereby improving erase operation efficiency and controllability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enhances integration intensity and erase efficiency by allowing direct voltage application to channels for hole injection, improving data erasure while maintaining low resistance in bit and source lines, thus overcoming limitations of existing structures.
Implementation Method 1
an erase operation by the F-N tunneling method in which a high voltage is applied to the substrate body to inject holes in a floating gate of a memory cell
Implementation Method 2
ion implantation regions formed in the active regions, connecting the channels of the first and second vertical strings by the ion implantation regions during program and reading operations
Data Source
AI summary
A non-volatile memory device includes a semiconductor substrate having active regions formed of a p-type semiconductor, first and second vertical strings disposed on the active regions, channels extending vertical to the semiconductor substrate, and a plurality of memory cells stacked along the channels, wherein the active regions are directly connected to the channels of the first and second vertical strings.