Multi-peak NDT Device for Multi-valued Logic
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Solution Overview
Problem
Existing negative differential transconductance devices typically exhibit only a single peak and valley, limiting their functionality and requiring complex processes at nano scales, which operate only at low temperatures and are not scalable for multi-valued logic applications.
Innovation Solution
A method involving semiconductors with different band structures, adjustable permittivity and thickness of gate dielectric layers, and connected devices with varying threshold voltages to create a multi-negative differential transconductance device capable of producing multiple peaks and valleys, enabling the implementation of multi-valued logic circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a heavily doped p-n-p or n-p-n junction structure is used to achieve negative differential transconductance, then the interband tunneling section is reduced and the NDT characteristic is implemented, but only a single peak and valley is achieved and the current consistently increases after passing the decrease section
Solution Approach 1:
The device is divided into multiple semiconductor regions (first, second, and third semiconductors) with different threshold voltages connected in series. Each region contributes a separate peak and valley to the overall transfer characteristic, transforming a single-peak device into a multi-peak device capable of multi-valued logic operations.
Solution Approach 2:
Different semiconductor materials or doping concentrations are used in different regions to create locally distinct threshold voltages. This local variation in electrical properties enables each region to contribute differently to the overall transfer characteristic, producing multiple peaks and valleys.
2Reliability
If an RTT structure or SET structure with quantum well is used to adjust energy level position and form peak current, then the NDT may be implemented, but the device size is several nano scales, the process is complex, and it operates only at low temperature
Solution Approach 1:
The invention replaces complex quantum well structures requiring nanoscale fabrication with a simpler series-connected multi-semiconductor structure that can be manufactured using conventional semiconductor processes, effectively substituting a complex 'expensive' structure with a simpler 'cheaper' alternative.
Solution Approach 2:
The invention changes the operating parameters by using semiconductors with different threshold voltages instead of relying on quantum confinement effects. This parameter change allows the device to operate at higher temperatures and simplifies the fabrication process while maintaining the NDT characteristic.
3Reliability
If n-type and p-type semiconductor materials are bonded to adjust channel layer conductivity or energy barrier to implement NDT phenomenon, then the NDT is achieved, but only a single peak and valley is implemented
Solution Approach 1:
The device is divided into multiple semiconductor regions (first, second, and third semiconductors) with different threshold voltages connected in series. Each region contributes a separate peak and valley to the overall transfer characteristic, transforming a single-peak device into a multi-peak device capable of multi-valued logic operations.
Solution Approach 2:
The invention uses composite semiconductor structures with different materials or doping characteristics to create distinct threshold voltages in series-connected regions. This composite approach enables multiple peaks and valleys in the transfer characteristic while maintaining the NDT phenomenon.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution allows for the creation of a multi-negative differential transconductance device with multiple peaks and valleys, facilitating the development of quaternary inverters and memory without significant area increase, achieving low power consumption, reduced size, and high speed.
Implementation Method 1
a gate insulating layer formed by being laminated on the substrate conductive portion
Implementation Method 2
the current decreases despite the increase in the gate voltage, so that a gate voltage-drain current characteristic curve is shown as an 'N' shape
Data Source
AI summary
A multi-negative differential transconductance device includes a substrate conductive portion; a gate insulating layer formed by being laminated on the substrate conductive portion; a first semiconductor, a second semiconductor, and a third semiconductor which have different threshold voltages and are formed to be horizontally connected in series on the gate insulating layer; and an electrode formed at both ends of the first semiconductor and the third semiconductor. The multi-negative differential transconductance device forms a junction of three or more semiconductor materials in one device to have a plurality of peaks and valleys so that the multi-negative differential transconductance device is utilized to implement a multi-valued logic circuit which is capable of representing four or more logical states without significantly increasing an area of the negative differential transconductance device which occupies the chip. Therefore, effects of low power consumption, a reduced size, and high speed of a chip may be achieved.