FinFET Memory Testing Multiple Read Operations Dynamic Faults
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Solution Overview
Problem
Existing testing methodologies for FinFET-based memory arrays are inadequate in detecting dynamic faults, particularly as fabrication process feature sizes decrease, and do not account for FinFET-specific faults that are not anticipated in planar-based memory test algorithms.
Innovation Solution
Implementing a novel set of March-type test patterns that include multiple sequential read operations after writing logic values into FinFET cells, with specific sequences of write and read operations to detect a wide range of dynamic faults, and incorporating initial read operations to verify logic values before write sequences, allowing for detection of both known and unknown faults.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional planar SRAM testing methodologies are used on FinFET-based memory arrays, then existing test algorithms can be applied without modification, but dynamic faults specific to FinFET architecture cannot be detected
Solution Approach 1:
The patent modifies test algorithm parameters by implementing multiple sequential read operations (e.g., reading the same cell 3-5 times) and adjusting write-read sequence patterns to specifically sensit化 FinFET dynamic faults such as threshold voltage shifts and leakage currents that differ from planar SRAM characteristics
Solution Approach 2:
The test algorithm is segmented into distinct phases: initial read operations to detect stuck-at faults, write operations to set known states, and multiple sequential read operations to detect dynamic faults, allowing each phase to target specific fault types unique to FinFET architecture
2Productivity
If feature size is reduced to improve manufacturing cost and integration density, then more memory cells can be packed into the same area, but dynamic faults become more prevalent and harder to detect
Solution Approach 1:
The test algorithm performs preliminary write operations to set known logic states in memory cells before executing multiple sequential read operations, enabling detection of dynamic faults that manifest only under specific state transitions and holding conditions relevant to scaled FinFET devices
Solution Approach 2:
The patent implements periodic read operations at defined intervals after write operations, creating a structured sequence that sensitizes and detects dynamic faults such as threshold voltage drift and leakage currents that occur over time in scaled FinFET memory cells
3Reliability
If multiple sequential read operations are implemented to detect dynamic faults, then fault detection sensitivity increases, but test time and operational complexity increase
Solution Approach 1:
The patent applies partial action by performing multiple read operations only on cells that fail initial single-read tests or are suspected of having dynamic faults, rather than uniformly applying multiple reads to all cells, thus reducing overall test time while maintaining detection sensitivity for problematic cells
Data Source
AI summary
A test methodologies for detecting both known and potentially unknown FinFET-specific faults by way of implementing an efficient and reliable base set of March elements in which multiple sequential March-type read operations are performed immediately after logic values (i.e., logic-0 or logic-1) are written into each FinFET cell of a memory array. For example, a March-type write-1 operation is performed, followed immediately by multiple sequentially-executed March-type read-1 operations, then a March-type write-0 operation is performed followed immediately by multiple sequentially-executed March-type read-0 operations. An optional additional March-type read-0 operation is performed before the March-type write-1 operation, and an optional additional March-type read-1 operation is performed before the March-type write-0 operation. The write-1-multiple-read-1 and write-0-multiple-read-0 sequences are performed using one or both of an increasing address order and a decreasing address order.