Stacked Semiconductor Layers in Nonvolatile Memory Devices
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Solution Overview
Problem
NAND type nonvolatile memory devices face challenges in increasing memory capacity while maintaining a compact form factor, as the number of memory cell transistors increases, leading to potential area expansion and operational inefficiencies.
Innovation Solution
The implementation of multiple stacked semiconductor layers with serially connected memory cell transistors, first and second selection transistors, and contact plugs to form a current path, allowing for increased memory capacity without expanding the device area, through a laminated structure and strategic placement of word lines, impurity regions, and insulating layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cell transistors is increased to increase memory capacity, then the memory capacity is improved, but the device area expands
Solution Approach 1:
The patent transitions from a planar two-dimensional arrangement of memory cell transistors to a three-dimensional stacked structure with multiple semiconductor layers. Memory cell transistors are distributed across multiple stacked layers, allowing the same device footprint to accommodate significantly more transistors by utilizing the vertical dimension. This dimensional change directly resolves the contradiction by increasing memory capacity without expanding the horizontal device area.
2Quantity of substance
If multiple stacked semiconductor layers are used to increase memory capacity, then the integration is improved, but the device complexity increases
Solution Approach 1:
The patent divides the memory device into multiple discrete semiconductor layers, each containing a portion of the memory cell transistors. This segmentation allows for modular manufacturing and assembly, where each layer can be processed and tested independently before being stacked. The segmentation approach manages device complexity by breaking down the complex three-dimensional structure into simpler, more manageable two-dimensional layers that can be fabricated using existing planar processing techniques.
3Reliability
If contact plugs are used to connect impurity regions across semiconductor layers, then the reliability is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent introduces contact plugs as intermediary elements that bridge the impurity regions across different semiconductor layers. These contact plugs serve as reliable electrical connectors that compensate for potential misalignments between layers. By using this intermediary structure, the system achieves reliable electrical connection without requiring extremely tight manufacturing tolerances, thus improving reliability while managing the complexity of precise alignment across multiple stacked layers.
Data Source
AI summary
Provided is a nonvolatile memory device having a three dimensional structure. The nonvolatile memory device includes a plurality of stacked semiconductor layers and a plurality of memory cell transistors which is formed on each of a plurality of semiconductor layers and serially connected. Memory cell transistors disposed on different semiconductor layers are serially connected to include one cell string forming a current path in a plurality of semiconductor layers, a first selection transistor serially connected to one edge portion of the cell string and a second selection transistor serially connected to the other edge portion of the cell string.