Top Gate TFT Two-Gate Structure for Off-Current Suppression
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Solution Overview
Problem
Conventional top-gate TFT structures with amorphous silicon active layers are not optimal for mid-mobility materials like microcrystalline silicon, leading to high off-current levels due to large field influence and defect density, which restricts the ON/OFF current ratio improvement.
Innovation Solution
A two-gate structure is introduced, featuring independent control of the gate/contact overlap region using a main and secondary gate, reducing the electric field at the contact area and allowing for better contact between the channel and source/drain regions, thereby suppressing off-current without requiring high-resolution photolithography.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional top-gate TFT structure with gate/contact overlap is used, then low contact resistance is achieved, but off-current increases due to large field influence in the overlap region
Solution Approach 1:
The gate electrode is divided into two separate gates: a first gate positioned over the channel region and a second gate positioned over the contact region. This segmentation allows independent control of the electric field in different regions, enabling low contact resistance in the overlap area while suppressing off-current through appropriate biasing of the second gate
Solution Approach 2:
Different gates are applied to different regions of the transistor: the first gate controls the channel region for proper switching operation, while the second gate specifically controls the contact region to minimize field-enhanced carrier generation. This local differentiation allows optimization of each region's electrical characteristics independently
2Speed
If mid-mobility material (μc-Si) is used as active layer, then effective mobility increases, but off-current increases due to smaller energy gap, higher mobility, and large defect density under large field
Solution Approach 1:
The second gate is positioned and biased to preemptively counteract the field-enhanced carrier generation that would otherwise occur in the contact region under high field conditions. By applying an appropriate voltage to the second gate before the harmful effect manifests, the structure prevents excessive off-current while allowing the μc-Si material's high mobility to benefit the ON-state current
3Object-generated harmful factors
If gate/contact overlap is reduced to suppress off-current, then off-current decreases, but contact resistance increases
Solution Approach 1:
The gate is segmented into two parts with the second gate specifically positioned over the contact region. This allows the gate structure to maintain overlap with the contact region (ensuring low contact resistance) while the second gate's independent biasing capability suppresses the electric field that would otherwise cause high off-current in the overlap area
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The two-gate structure significantly reduces off-current levels, achieving a three-order magnitude lower off-current compared to conventional devices, as demonstrated by device simulations, while maintaining compatibility with existing fabrication processes.
Implementation Method 1
operation in the off-state subjects the μc-Si active layer to very large field. The smaller energy gap, higher mobility, and large defect density in the active film result in off-current levels that are much higher than if a-Si is used.
Data Source
AI summary
A bottom-contacted top gate (TG) thin film transistor (TFT) with independent field control for off-current suppression is provided, along with an associated fabrication method. The method provides a substrate, and forms source and drain regions overlying the substrate, each having a channel interface top surface. A channel is interposed between the source and drain, with source and drain contact regions immediately overlying the source/drain (S/D) interface top surfaces, respectively. A first dielectric layer is formed overlying the source, drain, and channel. A first gate is formed overlying the first dielectric, having a drain sidewall located between the contact regions. A second dielectric layer is formed overlying the first gate and first dielectric. A second gate overlies the second dielectric, located over the drain contact region.