Buried Bit Line Air Gaps Reduce Parasitic Capacitance
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Solution Overview
Problem
Existing semiconductor devices with buried bit lines face challenges in reducing parasitic capacitance between adjacent bit lines, which hinders normal device operation as the integration density increases and the distance between bit lines narrows.
Innovation Solution
The method involves etching a semiconductor substrate to form bodies separated by trenches, creating a protective layer with open parts to expose sidewalls, and forming buried bit lines by silicidizing these exposed portions, followed by gap-filling the trenches with a dielectric layer to define air gaps between adjacent bit lines, thereby reducing parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If integration density is increased and distance between bit lines is narrowed, then productivity and integration are improved, but parasitic capacitance increases and device operation is hindered
Solution Approach 1:
The patent extracts the harmful dielectric material from the trench region between bit lines and replaces it with air gaps. By removing the solid dielectric filling and retaining only the essential structural components, the parasitic capacitance between adjacent bit lines is significantly reduced while maintaining the high integration density layout.
Solution Approach 2:
The patent introduces air gaps (porous structure) between adjacent bit lines instead of using solid dielectric material. This porous approach reduces the dielectric constant in the trench region, thereby reducing parasitic capacitance between bit lines while preserving the compact high-density architecture.
2Ease of manufacture
If conventional dielectric filling is used in trenches, then manufacturing simplicity is maintained, but parasitic capacitance between adjacent bit lines increases
Solution Approach 1:
The patent removes the conventional dielectric filling from the trenches between bit lines and replaces it with air gaps. This extraction of the harmful dielectric material reduces parasitic capacitance while the air gap formation process integrates seamlessly with existing manufacturing techniques, maintaining ease of manufacture.
Solution Approach 2:
The patent changes the dielectric parameter in the trench region from solid dielectric material (high dielectric constant) to air gaps (low dielectric constant). This parameter change significantly reduces parasitic capacitance between adjacent bit lines while the process remains compatible with standard manufacturing procedures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces parasitic capacitance between buried bit lines, improving device operation by enhancing integration density and reducing resistance through the use of metal silicide buried bit lines and air gaps.
Implementation Method 1
forming buried bit lines by silicidizing exposed portions of the bodies through the open parts
Data Source
AI summary
A method for fabricating a semiconductor device includes: etching a semiconductor substrate and forming a plurality of bodies separated from one another by a plurality of trenches; forming a protective layer with open parts to expose both sidewalls of each of the bodies; forming buried bit lines in the bodies by silicidizing exposed portions of the bodies through the open parts; and forming a dielectric layer to gap-fill the trenches and define air gaps between adjacent buried bit lines.