Fin-like Protrusion Floating Gate Memory for High Current Drive
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Solution Overview
Problem
Existing integrated circuits, such as NAND memories with floating gates, face challenges in scaling to low voltage operation due to limited current drive and compromised data retention, and there is a need for alternative memory structures and fabrication methods to achieve smaller features without increasing cell size.
Innovation Solution
The use of fin-like protrusions in semiconductor substrates for memory cells, where the floating gate and control gate are positioned on multiple sides of the protrusion, increasing channel width and current drive without expanding the cell area, and new fabrication techniques that form narrow features without extensive photolithography, such as forming spacers on sidewalls and using them as masks to create narrow fins and substrate isolation regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the thickness of tunnel oxide is reduced to increase current drive, then current drive is improved, but data retention is compromised due to increased charge leakage
Solution Approach 1:
The patent introduces a third dimension by forming fin-like protrusions upward from the substrate surface. This vertical structure increases the channel width without expanding the planar cell area, thereby improving current drive while maintaining the original tunnel oxide thickness and data retention characteristics.
Solution Approach 2:
The floating gate structure is positioned to wrap around at least two sides of the fin-like protrusion, creating a nested configuration where the gate encompasses the channel region in multiple dimensions. This increases the effective channel width and current drive capability without requiring thinner oxide.
2Power
If the memory cell area is enlarged to increase current drive, then current drive is improved, but memory density decreases
Solution Approach 1:
The patent transitions from a two-dimensional planar channel to a three-dimensional vertical fin structure. By increasing the fin height, the channel width is effectively increased, providing higher current drive while keeping the memory cell footprint unchanged, thus maintaining high memory density.
Solution Approach 2:
The channel region is segmented into multiple sides along the fin-like protrusion, with the floating gate positioned on at least two sides. This segmentation increases the total channel width without requiring a larger cell area, as the channel is distributed around the vertical fin structure.
3Manufacturing precision
If photolithography is used to form narrow features, then manufacturing precision is limited by photolithographic resolution, but new fabrication methods are needed to achieve smaller features
Solution Approach 1:
The patent uses spacer structures as intermediary elements in the fabrication process. Spacers are formed on the sidewalls of the fin-like protrusions and serve as masks for subsequent etching steps. This intermediary approach enables the formation of narrow features with dimensions below the photolithographic resolution limit.
Solution Approach 2:
The patent replaces direct photolithographic patterning with a self-aligned spacer-based patterning method. Instead of relying on photolithographic resolution to define narrow features, the process uses conformal spacer deposition and anisotropic etching to create precisely defined narrow structures through physical and chemical means.
Data Source
AI summary
A floating gate memory cell's channel region (104) is at least partially located in a fin-like protrusion (110P) of a semiconductor substrate. The floating gate's top surface may come down along at least two sides of the protrusion to a level below the top (110P-T) of the protrusion. The control gate's bottom surface may also comes down to a level below the top of the protrusion. The floating gate's bottom surface may comes down to a level below the top of the protrusion by at least 50% of the protrusion's height. The dielectric (120) separating the floating gate from the protrusion can be at least as thick at the top of the protrusion as at a level (L2) which is below the top of the protrusion by at least 50% of the protrusion's height. A very narrow fin or other narrow feature in memory and non-memory integrated circuits can be formed by providing a first layer (320) and then forming spacers (330) from a second layer without photolithography on sidewalls of features made from the first layer. The narrow fin or other feature are then formed without further photolithography in areas between the adjacent spacers. More particularly, a third layer (340) is formed in these areas, and the first layer and the spacers are removed selectively to the third layer. The third layer is used as a mask to form the narrow features.