Floating Gate Tip Formation via Pattern Duplication
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Solution Overview
Problem
The existing split-gate non-volatile memory devices face challenges with the over-erase problem due to stacked gate structures, and the use of a LOCOS structure leads to bird's beaks and aggressive growth, narrowing the process window and affecting erasing performance.
Innovation Solution
The method involves forming floating gates with tip corners by pattern duplication instead of a LOCOS structure, eliminating the need for thermal oxidation and reducing the thermal budget, thereby enhancing erasing performance and widening the process window.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a LOCOS structure is used to form floating gates, then thermal oxidation can be performed, but bird's beaks and aggressive growth occur which narrow the process window and affect erasing performance
Solution Approach 1:
The patent extracts and eliminates the LOCOS structure from the fabrication process, replacing it with a direct pattern transfer method using hard mask layers. This removal of the problematic LOCOS structure prevents the formation of bird's beaks and aggressive growth, thereby resolving the harmful effects while maintaining floating gate formation capability
Solution Approach 2:
The patent uses pattern duplication where the hard mask layer pattern is directly copied to the floating gate structure through conformal deposition and etching processes. This copying approach achieves precise floating gate formation without requiring thermal oxidation, eliminating the source of bird's beaks and aggressive growth
2Temperature
If a LOCOS structure is used for floating gate formation, then thermal oxidation is enabled, but the process window is narrowed
Solution Approach 1:
The patent replaces the thermal oxidation process (thermal/chemical system) with a low-temperature conformal deposition and etching process (mechanical/physical system). This substitution eliminates the need for high-temperature thermal oxidation while achieving the same floating gate formation result, thereby widening the process window and improving adaptability
Solution Approach 2:
The patent changes the temperature parameter from high-temperature thermal oxidation to low-temperature conformal deposition and etching. This parameter change maintains the floating gate formation functionality while avoiding the narrow process window associated with thermal oxidation, thus improving process versatility
3Ease of operation
If stacked gate structures are used, then memory device functionality is achieved, but over-erase problems occur
Solution Approach 1:
The patent segments the gate structure into distinct floating gate and control gate components with precise spatial separation. By using pattern duplication to create well-defined floating gate regions separated from control gates, the segmented structure prevents charge interference that causes over-erase problems while maintaining memory functionality
Solution Approach 2:
The patent uses conformal deposition processes (similar to pneumatic/hydraulic principles in terms of uniform distribution) to create evenly thick dielectric layers that precisely define the boundaries between floating gate and control gate regions. This uniform deposition ensures proper charge confinement and prevents over-erase while maintaining device functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the precision of floating gate formation, reduces thermal budget, and achieves improved performance and reliability by directly duplicating the upper surface profiles and critical dimensions from the hard mask features, resulting in enhanced erasing performance and a wider process window.
Implementation Method 1
etching the hard mask layer to form a recess in the hard mask layer
Implementation Method 2
etching the recessed feature and the floating gate layer to form a floating gate
Implementation Method 3
depositing a dielectric layer over the floating gate
Data Source
AI summary
A method for fabricating a memory device is provided. The method for fabricating a memory device includes forming a first dielectric layer over a substrate and forming a floating gate layer over the first dielectric layer. The method further includes forming a hard mask layer over the floating gate layer and etching the hard mask layer to form a recess in the hard mask layer. The method further includes patterning a portion of the hard mask layer under the recess to form a recessed feature having a first tip corner and etching the recessed feature and the floating gate layer to form a floating gate having a second tip corner. The method further includes depositing a second dielectric layer over the floating gate and forming a control gate partially over the floating gate and separating from the floating gate by the second dielectric layer.