Antifuse Memory Driving Circuit for Timing-Safe Programming
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing antifuse-type non-volatile memory technologies face issues with potential damage to memory cells and program disturbances due to signal timing differences between program and conducting voltages, leading to program failure.
Innovation Solution
The design incorporates a driving circuit that includes a bit line driver, word line driver, and antifuse control line drivers, with the following control lines receiving a conducting voltage throughout the program mode to prevent damage and disturbances, and eliminates the need for additional FL drivers, simplifying the circuit structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If signal timing differences between program and conducting voltages are not controlled, then circuit structure remains simple, but memory cells may be damaged and program disturbances occur
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit line to a specific voltage level before the program operation begins. This preliminary voltage setup ensures that when the program voltage is applied to the antifuse transistor, the timing differences between program and conducting voltages are automatically compensated, preventing memory cell damage without requiring complex timing control circuits.
Solution Approach 2:
The patent implements self-service through a self-compensating mechanism where the circuit automatically adjusts for timing differences between program and conducting voltages. The bit line driver and voltage timing control circuit work together to ensure that voltage transitions are synchronized, eliminating the need for external timing adjustment mechanisms and maintaining circuit simplicity while ensuring reliable programming.
2Reliability
If additional FL drivers are added to control signal timing, then program disturbances are reduced, but circuit size and complexity increase
Solution Approach 1:
The patent merges the functions of multiple drivers into a single integrated bit line driver that handles both the program voltage application and the conducting voltage control. By combining these functions and implementing a unified voltage timing control mechanism, the patent reduces the number of separate driver circuits needed while maintaining programming reliability and preventing program disturbances.
Solution Approach 2:
The bit line driver is designed with multi-functionality to perform multiple tasks: it controls the program voltage timing, manages the conducting voltage synchronization, and compensates for timing differences all through a single circuit block. This universal design eliminates the need for separate FL drivers while ensuring reliable programming operation.
3Reliability
If program voltage is applied without timing control, then circuit operation is fast, but memory cells suffer damage and program failure occurs
Solution Approach 1:
The patent employs periodic action through controlled voltage pulsing sequences. The program voltage and conducting voltage are applied in synchronized periodic cycles with precisely controlled durations and timing relationships. This periodic voltage application ensures that memory cells receive the necessary programming stress only during controlled time windows, preventing damage while maintaining efficient programming speeds.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach prevents damage to memory cells and reduces program disturbances, ensuring reliable programming without increasing circuit size or complexity.
Implementation Method 1
the voltage stress withstood by the antifuse transistor MAF is equal to the program voltage VPP. Under this circumstance, a gate dielectric layer of the antifuse transistor MAF is ruptured
Data Source
AI summary
An antifuse-type non-volatile memory includes a memory cell array, a driving circuit, a first voltage power supply and a second voltage power supply. The memory cell array includes a first sub-array and a second sub-array. All memory cells in the first sub-array are connected with a first antifuse control line and a first following control line. All memory cells in the second sub-array are connected with a second antifuse control line and a second following control line. The first voltage power supply provides a first voltage to the first antifuse control line and the second antifuse control line through a first antifuse control line driver and a second antifuse control line driver of the driving circuit. The second voltage power supply provides a second voltage to the first following control line and the second following control line directly.