Anti-fuse Array Segmented Program Gates
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Solution Overview
Problem
The challenge is to enhance the integration of anti-fuse arrays in semiconductor devices while maintaining performance characteristics, as the increasing number and size of fuses lead to increased chip area, and ensuring high-quality oxide films to prevent current leakage and successful programming.
Innovation Solution
The anti-fuse array is designed with program gates formed in an island shape and spaced apart by a slit region, allowing for improved program efficiency without increasing the program gate area, and featuring a method to determine the programmed state by rupturing the gate insulation film of at least one program gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of fuses and size of each fuse are increased, then the programming capability and reliability are improved, but the chip area occupied by the anti-fuse increases
Solution Approach 1:
The program gate is divided into two separate island-shaped gates instead of one continuous gate. This segmentation allows both gates to be programmed independently, doubling the programming success rate while occupying the same chip area as a single gate would require.
2Reliability
If the program gate area is increased to improve programming reliability, then the programming success rate is improved, but the chip area increases
Solution Approach 1:
The program gate is segmented into two separate island-shaped gates positioned at different locations. Each gate can be independently programmed, providing redundancy that doubles the success rate without requiring a larger total gate area.
Solution Approach 2:
Instead of increasing the area of a single program gate, the solution distributes two smaller gates across different spatial locations. This dimensional distribution achieves improved reliability without increasing the footprint of individual gate structures.
3Productivity
If a high voltage is applied to the program gate to rupture the gate insulation film, then the programming operation is completed, but current leakage may occur if the oxide film quality is insufficient
Solution Approach 1:
The patent employs a two-step programming approach where a first program operation is attempted, followed by a second program operation if the first succeeds. This preparatory redundancy ensures that if one programming attempt fails to properly rupture the film, the second attempt can compensate, preventing leakage issues.
Solution Approach 2:
The programming operation includes a verification step where the programmed state is determined after the gate insulation film rupture. This feedback mechanism allows the system to confirm successful programming and prevent leakage by ensuring proper film rupture before considering the operation complete.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design achieves improved program efficiency and doubles the programming success rate without increasing the chip area, allowing for more efficient integration of anti-fuse arrays in semiconductor devices.
Implementation Method 1
When a high voltage is applied to the program gate of the program transistor, the gate insulation film of the program gate ruptures due to the voltage difference between the high voltage program gate and the low voltage bit line
Data Source
AI summary
An anti-fuse, an anti-fuse array and a method of operating the same are disclosed. The anti-fuse array includes: an active region formed in a semiconductor substrate; a slit region formed at both edge portions of the active region in a first direction; a plurality of select gates extending in a second direction perpendicular to the first direction of the active region, and coupled to a select word line; a plurality of first program gates spaced apart from the select gates, formed over the active region isolated by the slit region, and coupled to a first program word line; a plurality of second program gates spaced apart from the select gates, formed over the active region isolated by the slit region, and coupled to a second program word line; and a bit line perpendicular to the select word line.