Configurable Logic Devices Using Antifuse and TSV
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Solution Overview
Problem
The increasing cost of mask sets and limited flexibility in semiconductor fabrication, particularly for custom products, due to the need for multiple expensive mask sets to accommodate various designs and higher data transfer rates, lead to high development costs and inefficient use of silicon area in FPGA devices.
Innovation Solution
The use of re-programmable antifuse technology in conjunction with Through Silicon Via (TSV) to construct configurable logic devices, allowing for the creation of modular systems with improved silicon area utilization and reduced mask costs, by employing transistors above or below antifuse configurable interconnect circuits, and integrating memory and I/O functions within the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple custom mask sets are used to accommodate various designs, then design flexibility is improved, but manufacturing cost increases exponentially
Solution Approach 1:
The patent implements a universal master slice structure that can be configured through programming to perform multiple different logic functions. This single reconfigurable structure replaces the need for multiple custom mask sets, allowing the same physical hardware to adapt to different design requirements through software configuration rather than physical remanufacturing
Solution Approach 2:
The invention introduces dynamic reconfigurability where the logic array can be programmed and reprogrammed at different times (e.g., configuration memory loaded during system initialization). This dynamic adaptation allows the device to change its functionality without physical modification, resolving the contradiction between design flexibility and manufacturing cost
2Adaptability or versatility
If dedicated mask sets are created for each custom product, then product customization is improved, but development time increases
Solution Approach 1:
The patent pre-configures a standard logic array structure with all necessary interconnect elements and master slices before deployment. This preliminary structuring allows rapid customization through programming rather than time-consuming mask fabrication and physical assembly, significantly reducing development time while maintaining customization capability
3Ease of manufacture
If generic Master Slice structures are used across multiple products, then manufacturing cost is reduced, but adaptability to specific designs decreases
Solution Approach 1:
The patent allows different regions or slices of the logic array to be configured with different parameters (such as different numbers of inputs, different logic functions, different interconnect patterns). This local configurability enables each master slice to be optimized for specific design requirements while using the same generic physical structure, achieving both cost efficiency and design adaptability
Data Source
AI summary
A system includes a semiconductor device. The semiconductor device includes a first semiconductor layer comprising first transistors, wherein the first transistors are interconnected by at least one metal layer comprising aluminum or copper. The second mono-crystallized semiconductor layer includes second transistors and is overlaying the at least one metal layer, wherein the second mono-crystallized semiconductor layer is less than 150 nm in thickness, and at least one of the second transistors is an N-type transistor and at least one of the second transistors is a P-type transistor.