Antifuse Contact Structure With Vertical Conductive Link Formation
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Solution Overview
Problem
The shrinking size of semiconductor devices poses challenges in processing antifuses and fuses due to the difficulty in forming conductive paths constrained by minimum design rule spacing between metal contacts, necessitating improved structures and methods.
Innovation Solution
The development of an antifuse structure with a first and second contact structure in a first interlevel dielectric layer, featuring a dielectric capping layer lining the opening between them, and a third contact structure with a conductive link extending through the dielectric capping layer, allowing for enhanced programming efficiency and integration of both antifuse and air gaps without being constrained by minimum design rules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If traditional antifuse structures are used with minimum design rule spacing between metal contacts, then device size can be reduced, but the conductive path length is constrained and programming becomes increasingly challenging
Solution Approach 1:
The patent introduces a vertical dimension by forming a recess in the interlevel dielectric layer and placing the third contact structure within this recess. This allows the conductive path to extend vertically through the dielectric capping layer, effectively increasing the conductive path length without increasing lateral spacing between contacts. The third contact structure's terminal electrode portion is positioned between vias of the first and second contact structures, utilizing the vertical space created by the recess to accommodate the extended conductive path.
2Area of moving object
If the spacing between metal contacts is reduced to shrink device size, then integration density improves, but forming reliable conductive links becomes more difficult
Solution Approach 1:
The patent introduces a dielectric capping layer as an intermediary between the first/second contact structures and the third contact structure. This capping layer lines the recess and provides a controlled interface for conductive link formation. The dielectric capping layer allows the conductive link to form reliably through a defined pathway, mediating the interaction between the contact structures and enabling reliable programming even with reduced contact spacing.
3Device complexity
If conventional antifuse structures are used, then manufacturing process is simpler, but programming efficiency is reduced and variations increase
Solution Approach 1:
The patent performs preliminary actions by pre-forming the recess in the interlevel dielectric layer and pre-lining it with the dielectric capping layer before forming the third contact structure. This preliminary preparation creates an optimized geometry for conductive link formation, ensuring that when programming occurs, the electric field is concentrated in the desired region, thereby improving programming efficiency and reducing variations.
4Productivity
If the conductive path length is increased to improve programming efficiency, then device area must increase, but this contradicts miniaturization goals
Solution Approach 1:
The patent resolves this contradiction by transitioning the conductive path from a purely lateral configuration to a vertical configuration. The third contact structure extends vertically within the recess, with its terminal electrode portion positioned between the vias of the first and second contact structures. This vertical arrangement allows the conductive path length to increase (improving programming efficiency) while the lateral footprint remains compact (maintaining miniaturization).
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed antifuse structure enables efficient programming with reduced variations and improved integration, overcoming spacing constraints and enhancing device performance by allowing for conductive links to form reliably across smaller features.
Implementation Method 1
a dielectric capping layer lining at least sidewalls of the opening
Implementation Method 2
A conductive link may extend between the first contact structure and the third contact structure and through the dielectric capping layer in the opening
Data Source
AI summary
A device includes an antifuse structure. The antifuse structure includes a first contact structure and a second contact structure in a first interlevel dielectric (ILD) layer, an opening arranged between the first contact structure and the second contact structure in the first ILD layer, and a dielectric capping layer lining at least sidewalls of the opening. A second ILD layer is arranged over the first ILD layer and in the opening. The second ILD layer lines the dielectric capping layer on at least the sidewalls of the opening. A third contact structure is arranged between the first contact structure and the second contact structure. The third contact structure includes a first portion in the opening.