APG Test Interface Circuit for 3D Memory Verification

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Solution Overview

Problem

Current methods for testing 3D memory devices in multi-core processor systems are complex and time-consuming, often generating invalid traffic patterns due to software bugs, which complicates the verification of reliable operation.

Innovation Solution

A test interface circuit with multiple algorithmic pattern generators (APGs) and an arbiter circuit that combine independent traffic streams to emulate multiple cores, allowing for robust and simplified testing by generating and merging traffic streams directly over a communication bus, preventing packet collisions and errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If software is used to generate pseudo-random traffic streams for testing, then traffic patterns can be generated, but the process becomes very complicated and time-consuming to write and maintain

Engineering Contradiction:

Improveease of test setupVSAvoidsoftware complexity

Core Design Contradiction:

Ease of manufactureVSDevice complexity

Solution Approach 1:

The patent replaces software-based traffic generation with hardware-based algorithmic pattern generators (APGs). The APGs are dedicated hardware circuits that generate traffic patterns directly, eliminating the need for complex software programs. This substitution of hardware for software resolves the contradiction by providing simpler, more maintainable test setup while reducing the complexity of test configuration.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The APGs are designed to be self-configuring and self-generating traffic patterns without requiring external software control. Each APG contains internal logic to generate realistic multi-core traffic patterns autonomously, reducing the need for manual software programming and maintenance while simplifying the overall test system setup.

Inventive Principle:

Principle #25Self-service

2Reliability

If software is used to generate traffic streams, then testing can be performed, but invalid patterns may be generated due to software bugs

Engineering Contradiction:

Improvetraffic pattern validityVSAvoidsoftware maintenance complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

Inventive Principle:

Principle #25Self-service

3Adaptability or versatility

If multiple independent traffic streams are generated to emulate multi-core systems, then realistic testing is achieved, but the testing system becomes more complex

Engineering Contradiction:

Improvemulti-core emulation capabilityVSAvoidtest interface complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent divides the test interface into multiple independent algorithmic pattern generators (APGs), with each APG responsible for generating traffic for a specific virtual core. This segmentation allows realistic multi-core emulation while keeping each APG relatively simple and modular. The segmented architecture resolves the contradiction by enabling complex multi-core testing capabilities through composition of simpler, independent units.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Each APG is designed as a universal module capable of generating traffic patterns for any virtual core in a multi-core system. The APGs can be configured to emulate different core behaviors and traffic patterns, providing versatile multi-core emulation capability without requiring separate specialized hardware for each core, thus managing complexity through reusability.

Inventive Principle:

Principle #6Universality (Multi-functionality)

4Reliability

If traffic streams are generated and merged, then comprehensive testing is achieved, but the time required for testing increases

Engineering Contradiction:

Improvetesting comprehensivenessVSAvoidtest execution time

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent implements continuous, concurrent traffic generation across multiple APGs, with each APG operating independently and continuously generating traffic patterns. The merged traffic streams provide comprehensive testing coverage without requiring sequential execution of different test scenarios, thus reducing total test execution time while maintaining thoroughness.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS10937518B2Multiple algorithmic pattern generator testing of a memory device

Publication Date: 2021.03.02 MICRON TECHNOLOGY INC

AI summary

Apparatuses including a test interface circuit that is configured to merge multiple independent traffic streams generated from individual algorithmic pattern generators (APGs) for communication with a memory device over a shared memory interface. The combination of multiple independent traffic streams, each with their own looping sequences and command timings, may generate a large set of random command sequences. The test interface circuit may include an arbiter circuit that merges a first independent traffic stream from a first APG and a second independent traffic stream from a second APG. Each of the first and second independent traffic streams are directed to different semi-independently-accessible portions of the memory device. The memory device may include a hybrid memory cube having independently accessible vaults or a high bandwidth memory device having independently accessible channels, in some examples. The test interface circuit may be included in a built-in self-test engine or in a standalone tester.