Arbitration Circuit for Uniform Data Transfer in Multi-Actuator Disk Drives

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Solution Overview

Problem

In magnetic disk devices with multiple actuator systems, existing technologies suffer from variations in data transfer speed due to prioritization of data transfers, leading to inconsistent write/read performance across different magnetic disks.

Innovation Solution

The implementation of an arbitration circuit in each controller to manage data transfers between actuator systems, ensuring equal data transfer speeds by arbitrating collisions and optimizing connection settings within the controller hardware configuration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If data transfer prioritization is implemented in multi-actuator systems, then data transfer speed for prioritized actuators is improved, but data transfer speed for non-prioritized actuators deteriorates

Engineering Contradiction:
Improvedata transfer speedVSAvoidoverall write/read performance consistency
Core Design Contradiction:
SpeedVSProductivity

Solution Approach 1:

The controller is divided into multiple independent controller chips, each managing specific actuator systems. This segmentation allows parallel data transfer operations across different actuators without mutual interference, eliminating the need for prioritization that causes speed variations.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

An arbitration circuit is introduced as an intermediary component to coordinate data transfers between multiple actuators and the buffer memory. The arbitration circuit fairly manages access rights, ensuring each actuator receives equitable data transfer opportunities without compromising overall system performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If multiple controller chips are connected in series to buffer memory, then connectivity to multiple actuators is achieved, but data transfer speed decreases for downstream controllers

Engineering Contradiction:
Improvecontroller connectivityVSAvoiddata transfer speed for downstream controllers
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

Each controller chip is equipped with its own arbitration circuit and buffer control circuit, creating independent control units. This segmentation prevents downstream controllers from being bottlenecked by upstream controllers, as each can independently manage its data transfers to the buffer memory.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The arbitration circuit performs preliminary arbitration before data transfers occur, allocating access rights in advance. This prevents downstream controllers from experiencing delays caused by upstream controllers' data transfer operations, ensuring consistent data transfer speeds across all controllers.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If arbitration circuit is added to each controller chip, then data transfer collision management is improved, but device complexity increases

Engineering Contradiction:
Improvedata transfer collision managementVSAvoidcontroller hardware configuration
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The arbitration function is segmented and distributed to each controller chip individually, rather than using a centralized arbitration mechanism. This approach improves reliability by allowing independent collision management at each controller while keeping the overall system architecture simple and modular.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11875824B2Magnetic disk device
Publication Date: 2024.01.16 KK TOSHIBA
  • US11875824B2 patent drawing
  • US11875824B2 patent drawing
  • US11875824B2 patent drawing

AI summary

According to an embodiment, each of a plurality of controller chips included in a magnetic disk device includes a buffer control circuit and an arbitration circuit, and controls a corresponding one of a plurality of actuator systems. The first controller chip is connected to a buffer memory via the buffer control circuit included in the first controller chip, and is connected to the second controller chip. The second controller chip is connected to the first controller chip and the third controller chip. The arbitration circuit included in the second controller chip performs arbitration between data transfer between the third controller chip and the first controller chip and data transfer between the first controller chip and an actuator system controlled by the second controller chip among the plurality of actuator systems.