Operational Speed Enhancement TRIZ Cases
- Fusion NPU Scheduling for Heterogeneous Sensor Data Locality
Data-locality scheduling in a fusion NPU cuts time and power when processing heterogeneous sensor inputs for autonomous driving.
- Parallel Search Unit Feedback for Faster Combinatorial Optimization
Multiple search units share best Ising-based solutions and restart from stronger state strings to improve optimization speed and hit rate.
- Dual-Scheduler WLAN Chip for Efficient Yet Updatable Processing
A dual-scheduler WLAN chip combines fixed hardware efficiency with programmable updates and accelerator-based scheduling for stable timing.
- Neural Network Accelerator Layer Scheduling via Shared Memory
Shared-memory layer handoff lets a host trigger each neural network layer in sequence while cutting host-accelerator transfer overhead.
- Dual-Scheduler Chip Architecture for Adaptive Hardware Accelerator Scheduling
A dedicated and a programmable scheduler coordinate hardware accelerators to balance fixed processing efficiency with WLAN standard adaptability.
- Programmable Network Interface Pipeline for Low-CPU Packet Processing
Hardware packet pipelines configured from bit file routing cut CPU load and compile time while speeding filtering, tunnelling, and routing.
- Multi-Turbo Stream Reception for ATSC Multipath Broadcasting
Parallel processing of multiple turbo streams improves ATSC reception in multipath channels while preserving compatibility with normal data streams.
- Neural Network Filter Circuit Stripes for Flexible Parallel Acceleration
Programmable filter circuit stripes and internal memory improve neural network execution speed while preserving flexibility across layer types.
- μOp Fusion Throttling for Producer-Consumer Port Pressure
Historical μop throttling blocks unhelpful producer-consumer fusion, easing fusion-port pressure to improve IPC and cut power.
- Temperature Scheduling for Energy-Based Optimization Search
Monitored energy updates identify suitable temperature ranges for simulated annealing and replica exchange, improving search efficiency.
- Hardware Accelerator Sleep-Polling to Cut CPU Cycle Waste
A delay-based sleep-polling scheme lets the CPU stop unnecessary accelerator checks, preserving cycles and improving multitasking performance.
- CXL Memory Expander for Metadata-Based Accelerator Data Allocation
Metadata-driven CXL memory expansion offloads accelerator data allocation from the CPU, cutting interrupts and repeated address transfers.
- Neural Network Layer Scheduling for Accelerator Idle-Time Reduction
Layer-wise scheduling uses accelerator idle-time estimates across neural network models to cut tail latency and raise throughput.
- Compute-in-Memory Column Thresholding for XNOR-Free Bit Cells
Column threshold adjustment replaces per-cell XNOR logic in compute-in-memory arrays, cutting transistor count, memory size, and power.
- Neural Network Kernel Allocation for Accelerator Resource Contention
Multiple candidate kernels are prebuilt per layer and selected by accelerator status to cut idle time and reduce contention.
- Systolic Tensor Array for Sparse Submatrix Zero-Bypass Computing
Bypassing zero values with significance map encoding lets a GPU tensor core handle sparse submatrix operations with less overhead.
- Accelerator Batch Sizing for On-Chip Memory-Limited Inference
Stage-wise batch sizing fits neural network inference to on-chip memory, cutting off-chip access cost and latency in accelerators.
- On-Chip Breakpoint Debugging Using Off-Chip Memory Output
Breakpoint output is written to off-chip memory so on-chip code can be debugged in real time across multiple breakpoints.
- Analog MAC Accelerator With Reconfigurable Switch Fabric
Segmented MAC operations and a programmable switch fabric help analog computing handle 32-bit cryptographic workloads with better precision.