Dual-Scheduler WLAN Chip for Efficient Yet Updatable Processing
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Solution Overview
Problem
Current WLAN chip technologies face high development difficulties, technical risks, and short life cycles due to fixed hardware implementations, while software implementations suffer from unpredictable processing delays and performance instability under strict time constraints.
Innovation Solution
A chip design incorporating a dedicated scheduler with a fixed processing procedure for high efficiency and a general scheduler with flexible programming for updates, along with multiple hardware accelerators connected through both hard and soft connections, allowing for adaptive scheduling and error handling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fixed hardware implementation is used, then processing efficiency is improved, but adaptability deteriorates
Solution Approach 1:
The chip is divided into two distinct schedulers: a dedicated scheduler with fixed hardware implementation for high-efficiency standard processing, and a general scheduler with programmable flexibility for adaptability. This segmentation allows each component to specialize in its strength while working together to resolve the contradiction between efficiency and adaptability.
Solution Approach 2:
The general scheduler is designed with multi-functionality to handle both standard WLAN protocols and updated standards through software programming. It can invoke hardware accelerators for common tasks while maintaining flexibility to adapt to new requirements, thus providing universal functionality that bridges the gap between fixed hardware and flexible software.
2Adaptability or versatility
If a software programmable implementation is used, then adaptability is improved, but processing efficiency deteriorates
Solution Approach 1:
Hardware accelerators serve as intermediaries between the general scheduler and actual data processing tasks. The general scheduler invokes these hardware accelerators for specific operations, combining the flexibility of software control with the high-speed processing of dedicated hardware circuits, thus resolving the efficiency-f Flexibility trade-off.
3Productivity
If a dedicated scheduler is used, then processing efficiency is improved, but ease of repair deteriorates
Solution Approach 1:
The system incorporates feedback mechanisms where the general scheduler can monitor the operation of hardware accelerators and the dedicated scheduler. When defects are detected, the feedback loop enables software-based adjustments and workarounds, making the system self-diagnosing and easier to repair while maintaining high processing efficiency through the dedicated scheduler.
Data Source
AI summary
A chip includes a dedicated scheduler, a general scheduler, and a plurality of hardware accelerators. The hardware accelerators are connected, at least one hardware accelerator is connected to the dedicated scheduler, and at least one hardware accelerator is connected to the general scheduler.