Programmable Network Interface Pipeline for Low-CPU Packet Processing
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Solution Overview
Problem
Current network interface devices face challenges in efficiently processing data packets due to high CPU usage and resource bottlenecks when performing operations like filtering and packet processing, which can lead to increased I/O bandwidth and memory consumption.
Innovation Solution
A network interface device with a hardware module comprising multiple processing units, each configured to perform specific operations in hardware, interconnected to form a pipeline for processing data packets, using a bit file description to configure the circuit for functions such as filtering, tunnelling, and routing, allowing parallel processing and reduced compile time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data packet processing is performed using traditional CPU-based methods, then flexibility and programmability are maintained, but CPU usage increases and processing speed decreases
Solution Approach 1:
The patent replaces CPU-based software processing with hardware-based processing using FPGAs and dedicated processing units. The compiler translates packet processing programs into hardware configurations that directly execute packet filtering, routing, and forwarding operations in hardware, eliminating the need for CPU intervention in data path operations and thereby reducing CPU usage while increasing processing speed.
Solution Approach 2:
The patent introduces a compiler as an intermediary that translates high-level packet processing programs into hardware-specific bitfiles. This compiler acts as a mediator between the software programming model and the hardware execution environment, enabling flexible packet processing without requiring direct CPU involvement in the actual packet forwarding operations.
2Productivity
If hardware modules are used for packet processing, then processing speed increases, but device complexity and compile time increase
Solution Approach 1:
The patent employs universal processing units that can be dynamically configured to perform different packet processing functions through software programming. The same hardware architecture can be reconfigured via the compiler to implement various packet filtering, routing, and forwarding algorithms, reducing the need for multiple specialized hardware components and thereby managing device complexity while maintaining high processing speeds.
3Adaptability or versatility
If routing information is provided for all processing units, then configurability increases, but compile time increases
Solution Approach 1:
The patent performs preliminary analysis and optimization during the compilation phase, where the compiler statically determines the routing configuration for processing units based on the packet processing program requirements. By pre-calculating and hardcoding the routing information into the hardware configuration before runtime, the system achieves high configurability without incurring runtime overhead, and the compile time is optimized through efficient algorithms that avoid exhaustive search of all possible routing combinations.
Data Source
AI summary
A method comprises receiving at a compiler a bit file description and a program, said bit file description comprising a description of routing of a part of a circuit. The method comprises compiling the program using said bit file description to output a bit file for said program.