Compute-in-Memory Column Thresholding for XNOR-Free Bit Cells
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Solution Overview
Problem
Conventional compute-in-memory systems for binary neural networks require XNOR operations at each bit cell, leading to increased layout area and power consumption due to the addition of transistors, which is undesirable.
Innovation Solution
Adjusting the activation threshold for each column of the compute-in-memory array to eliminate the need for XNOR functions in each bit cell, thereby reducing the number of transistors and improving power efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If XNOR operations are implemented at each bit cell, then the binary network's [-1,+1] basis can be transformed to the CMOS [0,1] basis, but the number of transistors per cell increases from six or eight to twelve, significantly increasing cell size and power consumption
Solution Approach 1:
The XNOR operation is extracted from the bit cell and relocated to a separate processing circuit. The bit cell now only performs MAC operations, while the XNOR transformation is handled externally, reducing the bit cell to its essential memory function and eliminating the need for additional transistors within the cell structure.
Solution Approach 2:
An intermediary processing circuit is introduced between the compute-in-memory array and the output. This intermediary handles the XNOR operation on the aggregated results from each bit line, serving as a mediator that performs the basis transformation without requiring modification of the fundamental bit cell structure.
2Reliability
If XNOR functions are included in each bit cell, then the basis transformation can be performed, but the layout area increases significantly due to the additional transistors
Solution Approach 1:
The XNOR function is extracted from the bit cell area and implemented in a shared processing circuit. This extraction removes the space-consuming transistor logic from each individual cell, allowing the memory array to maintain high density while the transformation capability is preserved in the readout circuitry.
Solution Approach 2:
The XNOR operations for all bit lines are merged into a single processing stage rather than being distributed across each bit cell. This consolidation allows shared use of processing resources and eliminates redundant circuitry, significantly reducing the total area required while maintaining the transformation capability.
3Reliability
If XNOR operations are performed at each bit cell, then the transformation from [-1,+1] to [0,1] basis is achieved, but power consumption increases due to the additional transistors
Solution Approach 1:
The power-consuming XNOR logic is extracted from each bit cell and consolidated into a single processing circuit. This extraction eliminates the continuous presence of additional transistors in the memory array, reducing static power consumption and dynamic power consumption during normal operation while preserving the transformation functionality.
Solution Approach 2:
Multiple XNOR operations that would individually consume power in separate bit cells are merged into a single processing stage. This merging reduces the total number of active transistors performing XNOR operations simultaneously, thereby reducing overall power consumption while maintaining the necessary transformation capability.
Data Source
Figure 1
Figure 2A~2C
Figure 2D
AI summary
A method performs XNOR-equivalent operations by adjusting column thresholds of a compute-in-memory array of an artificial neural network. The method includes adjusting an activation threshold generated for each column of the compute-in-memory array based on a function of a weight value and an activation value. The method also includes calculating a conversion bias current reference based on an input value from an input vector to the compute-in-memory array, the compute-in-memory array being programmed with a set of weights. The adjusted activation threshold and the conversion bias current reference are used as a threshold for determining the output values of the compute-in-memory array.