Neural Network Filter Circuit Stripes for Flexible Parallel Acceleration
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Solution Overview
Problem
Existing processor architectures are inefficient for performing complex neural network calculations, particularly in artificial intelligence applications, as they lack flexibility and optimal computational support for hidden layers.
Innovation Solution
A flexible neural network architecture incorporating a GSNN accelerator circuit with programmable circuit blocks that can adapt to different neural network types, including a filter circuit block with scalable filter stripes and a post-processing circuit block, working in parallel with a processor to enhance computational efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If current processor architectures are used for neural network calculations, then general-purpose computing is maintained, but execution efficiency and speed are insufficient
Solution Approach 1:
The processor is divided into multiple specialized circuit blocks including input circuit blocks, filter circuit blocks, and post-processing circuit blocks. Each block is responsible for specific neural network operations, enabling parallel processing and significantly improving calculation speed while maintaining manageable complexity through functional decomposition
Solution Approach 2:
The circuit blocks are designed with programmable features that allow them to perform multiple functions. The input circuit blocks can handle different input operations, filter circuit blocks can apply various filtering algorithms, and post-processing circuit blocks can execute different post-processing tasks, providing versatility without requiring separate dedicated hardware for each function
2Productivity
If specialized circuit blocks are introduced for neural network processing, then calculation efficiency is improved, but hardware flexibility for different neural network architectures is reduced
Solution Approach 1:
The circuit blocks incorporate programmable features that allow their behavior to be dynamically configured. Control registers and configuration mechanisms enable the same hardware block to adapt to different neural network architectures, layer types, and operational requirements, maintaining hardware flexibility while achieving specialized processing efficiency
Solution Approach 2:
Each circuit block is designed to perform multiple functions within its domain. The input circuit blocks can handle various input operations, filter circuit blocks can apply different filtering algorithms, and post-processing circuit blocks can execute multiple post-processing tasks, allowing a single hardware implementation to support diverse neural network architectures
3Speed
If multiple programmable circuit blocks are used for parallel processing, then processing speed is enhanced, but device complexity increases
Solution Approach 1:
The parallel processing architecture is segmented into distinct functional blocks (input, filter, post-processing) that can operate independently and concurrently. This segmentation enables parallel execution of multiple neural network operations simultaneously while keeping each individual block's complexity manageable through clear functional separation
Solution Approach 2:
Multiple circuit blocks are merged into a unified neural network processing system with standardized interfaces and control mechanisms. The blocks work together as an integrated system, sharing resources and coordinating through defined protocols, which reduces overall system complexity compared to having completely independent processing units
Data Source
AI summary
A system and an accelerator circuit includes an internal memory to store data received a memory associated with a processor and a filter circuit block comprising a plurality of circuit stripes, each circuit stripe including a filter processor, a plurality of filter circuits, and a slice of the internal memory assigned to the plurality of filter circuits, where the filter processor is to execute a filter instruction to read data values from the internal memory based on a first memory address, for each of the plurality of circuit stripes: load the data values in weight registers and input registers associated with the plurality of filter circuits of the circuit stripe to generate a plurality of filter results, and write a result generated using the plurality of filter circuits in the internal memory at a second memory address.