Dual-Scheduler Chip Architecture for Adaptive Hardware Accelerator Scheduling
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Solution Overview
Problem
Current WLAN chip technologies face high development difficulties, technical risks, and limited upgrade capabilities due to either full hardware implementation's inflexibility or full software implementation's unpredictable processing delays, which affect performance stability and adaptability to evolving standards.
Innovation Solution
A chip design incorporating a dedicated scheduler for fixed processing efficiency and a general scheduler for flexible software-programmable updates, along with multiple hardware accelerators connected through both hard and soft connections, allowing collaborative scheduling and adaptive handling of various application scenarios.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If full hardware implementation is used, then processing efficiency is improved, but adaptability to evolving standards deteriorates
Solution Approach 1:
The chip architecture is segmented into multiple hardware accelerators with different functions (FFT, channel estimation, equalization, decoding) and two types of schedulers (dedicated and general). This segmentation allows specific hardware components to handle standard processing efficiently while the general scheduler provides flexibility for new standards, resolving the contradiction between processing efficiency and adaptability.
Solution Approach 2:
The system implements dynamic scheduling where the general scheduler can dynamically allocate and coordinate hardware accelerators based on different technical standards and processing requirements. This dynamic allocation mechanism enables the chip to adapt to evolving standards while maintaining efficient processing through hardware acceleration, directly addressing the contradiction between fixed hardware efficiency and flexible adaptability.
2Adaptability or versatility
If full software implementation is used, then adaptability to evolving standards is improved, but processing delays become unpredictable
Solution Approach 1:
The dedicated scheduler acts as an intermediary between the software programmable general scheduler and the hardware accelerators. It provides deterministic scheduling for time-critical operations, ensuring predictable processing delays and stable performance, while the general scheduler handles high-level coordination and adaptability to different standards.
Solution Approach 2:
The system replaces pure software scheduling with a hybrid approach that uses dedicated hardware schedulers for time-critical path management. This substitution of mechanical/software control with hardware-based scheduling eliminates unpredictable software delays while maintaining adaptability through the programmable general scheduler, directly addressing the reliability issue.
3Productivity
If dedicated hardware schedulers are used, then processing efficiency is improved, but flexibility in handling new standards deteriorates
Solution Approach 1:
The system merges dedicated schedulers (for specific standard efficiency) with a general programmable scheduler (for flexibility). The general scheduler can dynamically allocate and coordinate the same hardware accelerators for different standards and applications, combining the advantages of both dedicated hardware efficiency and software flexibility to resolve the contradiction.
Solution Approach 2:
The general scheduler provides universal control over multiple hardware accelerators, enabling a single programmable unit to handle various technical standards and processing requirements. This multi-functionality allows the system to maintain high processing efficiency through hardware acceleration while adapting to new standards through software programming, directly addressing the flexibility issue.
4Adaptability or versatility
If multiple hardware accelerators are soft connected, then adaptability is improved, but connection complexity increases
Solution Approach 1:
The schedulers (both dedicated and general) act as intermediaries that manage the soft connections between hardware accelerators. They provide abstracted control interfaces that simplify the complexity of soft connections, allowing flexible adaptation to different standards while hiding the underlying connection complexity from higher-level control logic.
Data Source
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AI summary
A chip is disclosed, and belongs to the field of electronic technologies. The chip includes a dedicated scheduler, a general scheduler, and a plurality of hardware accelerators. The plurality of hardware accelerators are soft connected, at least one hardware accelerator is connected to the dedicated scheduler, and at least one hardware accelerator is connected to the general scheduler. The dedicated scheduler has a relatively fixed processing procedure, and processing efficiency is relatively high. The general scheduler has a relatively flexible processing procedure, and a hardware design defect can be overcome through software programming to improve performance. Therefore, processing flexibility of the chip can be achieved while processing efficiency of the chip is ensured.