Area Array Substrate Package with Exposed Conductors for Stacking

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Solution Overview

Problem

Existing semiconductor packaging technologies face challenges in achieving high yield and reliability due to the failure of one chip in multi-chip or chip stack packages, leading to reduced productivity and increased costs, particularly with the use of lead frame type packages rather than area array type packages.

Innovation Solution

An integrated circuit package system is developed, featuring an area array substrate with surface conductors, a molded package body with a step to expose surface conductors, and a film-assisted molding process to reduce epoxy usage, allowing for more efficient stacking and increased rigidity, thereby supporting multiple integrated circuits and reducing package height.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If multi-chip or chip stack packages are used to increase memory density and reduce package footprint, then device functionality and integration are improved, but yield and reliability deteriorate because failure of one chip causes the entire package to fail

Engineering Contradiction:

Improvedevice functionalityVSAvoidpackage yield

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The invention segments the package structure into a lead frame portion and a molded package body portion, allowing independent testing and replacement of individual chip segments while maintaining overall package functionality

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The lead frame acts as an intermediary component that provides mechanical support and electrical interconnection between multiple chips, enabling modular assembly where individual chips can be tested and replaced independently

Inventive Principle:

Principle #24Intermediary (Mediator)

2Ease of manufacture

If lead frame type packages are used for package stacking, then manufacturing simplicity is maintained, but terminal count and footprint efficiency are limited compared to area array type packages

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoidpackage footprint

Core Design Contradiction:

Ease of manufactureVSArea of stationary object

Solution Approach 1:

The invention merges the simplicity of lead frame packaging with the footprint efficiency of area array packages by integrating area array type surface conductors onto the lead frame structure, achieving both manufacturing ease and space efficiency

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The lead frame is designed to serve multiple functions: providing mechanical support, electrical interconnection, and serving as a substrate for area array surface conductors, thereby combining advantages of different package types

Inventive Principle:

Principle #6Universality (Multi-functionality)

3Area of stationary object

If area array type packages are used to increase terminal count and reduce footprint, then package density is improved, but manufacturing complexity increases compared to lead frame type packages

Engineering Contradiction:

Improvepackage footprintVSAvoidpackage structure

Core Design Contradiction:

Area of stationary objectVSDevice complexity

Solution Approach 1:

The invention applies local quality by implementing area array surface conductors only in specific regions where high density is required, while maintaining simpler lead frame structures in other areas, thereby optimizing the balance between density and manufacturability

Inventive Principle:

Principle #3Local quality

Data Source

PatentUS8409920B2Integrated circuit package system for package stacking and method of manufacture therefor

Publication Date: 2013.04.02 STATS CHIPPAC LTD

AI summary

An integrated circuit package system and method of manufacture therefor includes: forming an area array substrate; mounting surface conductors on the area array substrate; forming a molded package body on the area array substrate and the surface conductors; providing a step in the molded package body; and exposing a surface conductor by the step.