Bit-Level Verification in ARINC 429 Transmitter Modules

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Solution Overview

Problem

Existing methods for verifying ARINC communications, such as ARINC 429, require significant processing power and complex hardware to compare entire transmitted words, which is inefficient and costly.

Innovation Solution

A data verification method that compares individual bits transmitted over an ARINC 429 bus using a microcontroller with a transmitter interrupt handler and XGate co-processor, eliminating the need for separate verification hardware by utilizing bit-level comparison and wraparound techniques for real-time error detection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If entire transmitted words are compared for verification, then transmission accuracy is improved, but processing power requirements increase

Engineering Contradiction:

Improvetransmission accuracyVSAvoidprocessing power

Core Design Contradiction:

ReliabilityVSPower

Solution Approach 1:

The patent segments the 32-bit word into individual bits for separate verification. Instead of comparing entire words, the system verifies each bit independently as it is transmitted, significantly reducing the processing power required while maintaining transmission accuracy.

Inventive Principle:

Principle #1Segmentation

2Reliability

If complex hardware components are used for verification, then transmission accuracy is improved, but device complexity increases

Engineering Contradiction:

Improvetransmission accuracyVSAvoidhardware complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The transmitter module performs its own self-verification by comparing transmitted bits with received bits. This self-service approach eliminates the need for separate complex verification hardware, reducing device complexity while maintaining transmission accuracy through bit-level comparison.

Inventive Principle:

Principle #25Self-service

3Power

If bit-level comparison is used instead of word-level comparison, then processing power is reduced, but verification time increases

Engineering Contradiction:

Improveprocessing powerVSAvoidverification time

Core Design Contradiction:

PowerVSLoss of time

Solution Approach 1:

The patent implements continuous bit-level verification where each bit is compared immediately upon transmission and reception. This continuous verification process eliminates idle time between verifications and maintains system throughput, preventing any increase in overall verification time despite the bit-level granularity.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentEP2555123B1Bit transmission verification in an ARINC-based system

Publication Date: 2017.03.29 HAMILTON SUNDSTRAND CORP

AI summary

An example data verification method (80) includes communicating a bit from a transmitter module (12) to a receiver module (14) through a bus (16). The bit forms a portion of an ARINC word. The method verifies the bit at the bus (16) using the transmitter module (12).