Programmable Arithmetic Array Bus for In-Band Reconfiguration
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Solution Overview
Problem
Existing systolic array configurations in matrix product calculations require separate paths for data and configuration information, leading to inefficient use of resources and increased reconfiguration time as the scale of the array increases.
Innovation Solution
The proposed arithmetic operator uses a data bus to transmit both normal calculation data and reconfiguration data simultaneously, allowing for a time-slot scheme where transmission data is collectively sent to multiple processing elements (PEs) on the same data bus, eliminating the need for a dedicated configuration path and optimizing data transmission efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate configuration path is used to transmit reconfiguration data to processing elements, then the data bus can be dedicated solely to calculation data transmission, but the reconfiguration time increases and wiring complexity increases as the array scale increases
Solution Approach 1:
The patent merges the configuration path and data bus into a single shared transmission medium. Reconfiguration data and calculation data are multiplexed on the same data bus by transmitting them in different time slots, eliminating the need for separate configuration wiring and reducing reconfiguration time while maintaining transmission reliability through structured time-division multiplexing
Solution Approach 2:
The patent implements periodic time-division multiplexing where the data bus alternates between transmitting calculation data during calculation cycles and reconfiguration data during reconfiguration cycles. This periodic switching allows the same physical bus to serve dual purposes without interference, resolving the contradiction between dedicated transmission reliability and reconfiguration speed
2Ease of operation
If a separate configuration path is provided for transmitting reconfiguration data, then data and configuration can be transmitted independently, but the wiring cost and device complexity increase
Solution Approach 1:
The data bus is designed to serve multiple functions: it transmits both calculation data during operational cycles and reconfiguration data during reconfiguration cycles. This multi-functionality eliminates the need for separate dedicated configuration wiring, reducing wiring complexity while maintaining the ability to independently control data and configuration transmission through time-division multiplexing
Solution Approach 2:
The patent combines the configuration path functionality into the existing data bus infrastructure. By merging these two transmission paths into one shared resource with time-division multiplexing, the patent reduces wiring complexity and device complexity while preserving the operational independence of data and configuration transmission through structured time slot allocation
3Productivity
If the data bus transmits data to multiple processing elements simultaneously, then transmission efficiency improves, but data destined for different PEs must be managed at different cycles
Solution Approach 1:
The patent employs periodic time-division multiplexing to manage data transmission to multiple processing elements. Each PE is assigned specific time slots for receiving data, and the system periodically cycles through different PEs. This structured periodic approach improves transmission efficiency by fully utilizing the data bus while managing multi-PE data distribution through predictable, repeating patterns that simplify control logic
Data Source
AI summary
An arithmetic operator includes: multiple arithmetic elements each serving as a programmable circuit capable of programming a logical function; and a data bus that connects two or more of the multiple arithmetic elements and that transmits transmission data. The transmission data includes first data used in one of the two or more arithmetic elements and second data used to reconfigure a logical function of any one of the two or more arithmetic elements, the transmission data destined for each of the two or more arithmetic elements on the same data bus is collectively transmitted on the same data bus at a cycle different with each of the two or more arithmetic elements, and each arithmetic elements receives the first data and the second data for own arithmetic element by extracting the transmission data destined for the own arithmetic element at a cycle associated with the own arithmetic element.