Arithmetic Circuit with Parallel Binomial LUTs for Higher Throughput
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Solution Overview
Problem
Conventional product-sum arithmetic circuits using distributed arithmetic suffer from low throughput due to repeated LUT searches at each bit position, increased circuit scale from redundant memory elements, and high power consumption due to frequent LUT updates and redundant circuits.
Innovation Solution
An arithmetic circuit that performs parallel processing across all bit positions using an LUT generation circuit and distributed arithmetic circuits, eliminating the need for memory circuits and reducing redundant LUTs by dividing N-nomial product-sum arithmetic into binomial or complex number arithmetic operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If distributed arithmetic is used to avoid multiplication circuits, then device complexity is reduced, but throughput decreases due to repeated LUT searches at each bit position
Solution Approach 1:
The patent segments the N-nomial product-sum arithmetic into multiple binomial product-sum arithmetic operations. By dividing the computation into smaller binomial units (N/2 segments), the system can process multiple bit positions in parallel without requiring a full N-nomial LUT, thus maintaining simplicity while improving throughput through parallel execution of segmented operations.
Solution Approach 2:
The patent transitions from sequential bit-position processing to parallel processing by introducing a new dimension of computation. Instead of searching LUTs sequentially for each bit position, the system restructures the arithmetic into binomial operations that can be executed simultaneously across multiple bit positions, effectively adding a parallel processing dimension to the computation.
2Measurement precision
If LUT searches are performed for each bit position, then product-sum arithmetic accuracy is maintained, but the number of memory elements increases circuit scale
Solution Approach 1:
The patent segments the large N-nomial LUT into multiple smaller binomial LUTs. Each binomial LUT handles only 2 coefficients at a time, dramatically reducing the memory size required per LUT. By distributing the computation across N/2 binomial LUTs instead of one large N-nomial LUT, the system maintains arithmetic accuracy while reducing the circuit scale of individual memory elements.
Solution Approach 2:
The patent combines the results from multiple binomial LUT searches to achieve the final product-sum arithmetic result. By merging the outputs of N/2 binomial operations, the system reconstructs the accurate N-nomial result without requiring a single large N-nomial LUT, thus maintaining precision while reducing individual LUT size.
3Productivity
If redundant LUTs are created for parallel processing, then throughput increases, but power consumption increases due to redundant circuits
Solution Approach 1:
The patent segments the computation into binomial units that can be processed in parallel, enabling throughput improvement without requiring redundant full-scale N-nomial LUTs. Each binomial LUT is smaller and consumes less power, so parallel execution of multiple binomial LUTs achieves high throughput with lower total power consumption compared to redundant large LUTs.
Solution Approach 2:
The patent uses simplified binomial LUT copies instead of copying full N-nomial LUTs. By creating N/2 copies of small binomial LUTs rather than copying a large N-nomial LUT, the system achieves parallel processing capability with reduced redundancy. Each copied binomial LUT consumes minimal power, so the total power consumption of all copies is lower than redundant large LUTs while maintaining high throughput.
4Adaptability or versatility
If frequent LUT updates are performed to handle coefficient variations, then adaptability is improved, but power consumption increases due to update operations
Solution Approach 1:
The patent segments the coefficient handling into multiple binomial units, each with its own small LUT. When coefficients vary, only the specific binomial LUTs affected by the variation need to be updated, rather than updating a single large N-nomial LUT or all LUTs simultaneously. This segmented update approach reduces the total power consumption during LUT updates while maintaining adaptability to coefficient variations.
Data Source
AI summary
An arithmetic circuit includes an LUT generation circuit (1) that, when coefficients c[n] (n=1, . . . , N) are paired two by two, outputs a value calculated for each of the pairs, and a distributed arithmetic circuit (2-m) that calculates values y[m] of product-sum arithmetic, by which data x[m, n] of a data set X[m] containing M pairs of data x[m, n] is multiplied by the coefficients c[n] and the products are summed up, in parallel for each of the M pairs. The distributed arithmetic circuit (2-m) includes a plurality of binomial distributed arithmetic circuits that calculate the value of binomial product-sum arithmetic in parallel for each of the pairs, based on a value obtained by pairing N data x[m, n] corresponding to the circuit two by two, a value obtained by pairing the coefficients c[n] two by two, and the value calculated by the LUT generation circuit (1), and a binomial distributed arithmetic result summing circuit that sums up the values calculated by the binomial distributed arithmetic circuits and outputs the sum as y[m].