Arithmetic Logic Unit for Modular Addition Multiplication Sequences
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Solution Overview
Problem
Existing cryptographic implementations face inefficiencies in performing sequences of modular additions followed by a single modular multiplication, requiring optimization to reduce computational resources.
Innovation Solution
A computer processing system is designed with an arithmetic logic unit that includes addition and modular multiplication circuits, along with a sequencing unit to efficiently direct the output of addition operations to modular multiplication operations, thereby optimizing resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If modular multiplication is implemented using traditional methods (multiplication followed by Montgomery reduction or Barrett reduction), then modular multiplication can be performed, but the computational resources (gates and area) required increase significantly
Solution Approach 1:
The patent merges the addition circuit and modular multiplication circuit into a single integrated arithmetic logic unit, allowing the addition result to be directly fed into the modular multiplication circuit without requiring separate modular reduction operations. This integration eliminates the need for additional Montgomery or Barrett reduction circuits, thereby reducing the total computational resources required while maintaining modular multiplication capability.
Solution Approach 2:
The patent performs modular additions in advance within the arithmetic logic unit before the modular multiplication operation. By pre-computing the sum of multiple additions and feeding it directly into the modular multiplication circuit, the system avoids the need for separate modular reduction steps that would otherwise be required, thus reducing overall computational complexity.
2Productivity
If a sequence of modular additions followed by modular multiplication is implemented using separate circuits, then the operations can be performed, but the area and gate count increase
Solution Approach 1:
The patent combines multiple addition circuits and the modular multiplication circuit into a single integrated arithmetic logic unit. This merging allows the addition results to be directly utilized by the modular multiplication circuit without requiring separate modular reduction hardware, significantly reducing the total circuit area and gate count while maintaining computational efficiency.
Solution Approach 2:
The arithmetic logic unit is designed to perform multiple functions: it can execute sequences of modular additions and subsequently perform modular multiplication using the same hardware resources. This multi-functionality eliminates the need for dedicated separate circuits for each operation, thereby reducing the overall area required while maintaining high productivity.
Data Source
AI summary
A computer processing system that includes at least one arithmetic logic unit in a computer processing device and includes at least one addition circuit operably configured to compute addition operations, operably configured to receive two numerical inputs, and operably configured to compute a sum and includes at least one modular multiplication circuit operably configured to receive the sum from the at least one addition circuit, receive at least one other numerical input, and receive a numerical modulus to perform a modular multiplication operation and generate a modular multiplication operation result.