Computation Using Non-Contact Making Devices TRIZ Cases
- Sum of Addends Logic Circuit with Faithful Rounding
A logic circuit synthesizes a sum of addends operation using faithful rounding to discard less significant bits while maintaining known error profiles.
- Hierarchical Data Encoding Using Numerical Path Values
Calculating numerical values from mathematical series encodes hierarchical paths, eliminating recursive algorithms and reducing memory usage.
- FFT Processing-in-Memory Lane Mapping Eliminates Cross-Bank Traffic
Host processing units map fast Fourier transform elements to specific memory banks and lanes for direct execution by processing-in-memory hardware.
- Augmented Reality Document Annotation System
Automated annotation system overlays explanatory markers on displayed documents to enhance user comprehension of complex text.
- Pipelined Multiply-Scan Circuit Using Serial Shift Modules
Serially connected left-shift modules and adders in a pipelined architecture enhance multiply-scan processing efficiency while reducing power consumption.
- Matrix Calculation Device Partition Position Guidance
A matrix calculation device visually guides users through partition positions for efficient product calculations.
- Mixed Radix DFT Concurrent Reading and Calculation
A mixed radix DFT apparatus configures dual circulation parameters to enable concurrent data reading and calculation.
- Montgomery Multiplication Circuit Segmentation
A Montgomery multiplication circuit decomposes large binary numbers into smaller digits for efficient partial result calculation.
- Integrated Multiply-Accumulate Module for Fixed-Point and Floating-Point Operations
An integrated multiply accumulate module shares multipliers between fixed-point and floating-point units, reducing chip area and power consumption.
- Semiconductor Device Control Circuit for Power Supply Noise Suppression
Arithmetic circuit executes dummy operations to raise ground state current and reduce peak-to-ground variation.
- Mixed-Precision Memcomputing System for Computational Precision
A mixed-precision memcomputing system combines low-precision resistive memory with digital combinational circuitry to perform iterative computations.
- Matrix Multiplier MAC Cell Zero-Value Operation Disable
A matrix multiplier disables multiplication accumulation in MAC cells when input values are zero.
- Matrix Multiplication Circuit Module Using Time-Multiplexed Row-Column Calculation
A circuit module performs matrix multiplication using a row-column calculation unit with sequential electrical signal inputs.
- Reconfigurable Neural Network Architecture for Embedded Systems
A reconfigurable computer architecture integrates synaptic coefficient memories directly with computing units to minimize external data exchanges.
- Fast Vector Multiplication Circuit for Neural Network Accelerators
A fast vector multiplication circuit arranges multiplicands into scheduled operands using a scheduler and compressor to enhance parallelism.
- Masked Data Sign Indicator Circuit Without Unmasking
Circuit determines sign indicator bits from masked binary data using additive masking operations without unmasking.
- Vector Instruction for Complex Conjugate Multiplication
A vector friendly instruction format executes complex conjugate multiplication operations in a single cycle.
- Frequency Synthesis Using Primitive Integer Ratios and Common Reference Clock
A common reference ratio module generates integer divisor ratios for a clock synthesis unit using a single reference clock.
- Redundant Floating-Point Representation for Parallel Arithmetic
A redundant representation format accelerates floating-point operations by enabling parallel processing without extensive carry propagation.
- Rational Division Circuit Using Redundant Carry Signals
A rational division circuit generates precise k-bit quotients using weighted carry signals and multiplexers for binary inputs.
- Digital Audio Processing Device Sine Wave Detection
A digital audio processing device calculates correction values for local extrema in non-periodic signals to improve sound quality.
- Digital Filter Approximate Adders for ISI Compensation
Approximate adders in the least significant bits of a carry-save tree reduce power and area while maintaining signal integrity under inter-symbol interference.
- In-Memory Computing Shift Restoration Circuit for Power Reduction
Shift restoration circuit generates restored sum-of-products from shifted weight values, reducing bit line current and power consumption during computation.
- Matrix Operations Circuitry for Integrated Circuits
Shared multiplier and adder circuits merge Cholesky decomposition with forward substitution, reducing latency in large matrix equation solving.
- Base-2n In-Memory Adder Reducing Data Transport Power
A base-2n in-memory adder performs arithmetic directly within memory arrays using Perpetual Digital Perceptron storage.
- Single Adder Stage for Floating Point Rounding
A single adder stage computes rounded absolute values using look-up tables to determine intermediate bits.
- Arithmetic Logic Unit for Modular Addition Multiplication Sequences
Integrated arithmetic logic unit directs addition sums into modular multiplication circuits, reducing computational gate count and circuit area.
- Mixed Radix FFT on GPUs Using Parallel Radix-r Blocks
Factorizing input data into radix-r blocks enables parallel mixed radix FFTs on GPUs, resolving CPU inefficiencies and repetitive calculation bottlenecks.
- Affine Correction for Conductance Drift in Neuromorphic Crossbar Arrays
A correction unit applies affine transformations to output currents from crossbar arrays.
- Floating Point Carry-Save MAC Unit Pipeline Speed
A floating point carry-save multiply-add unit uses a segmented pipeline to accelerate BF16 and FP32 arithmetic operations.
- Automated Hydrocarbon Reservoir Forecasting via Unified Static Dynamic Modeling
Iterative model generation merges static and dynamic analyses to resolve the contradiction between high characterization accuracy and excessive processing time.