Base-2n In-Memory Adder Reducing Data Transport Power
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Solution Overview
Problem
In Von Neumann computing architecture, the power consumption and computational efficiency are hindered by the need for numerous bit-level manipulations and data transportations through bus-lines, leading to bus-line congestions and increased operational steps, especially when handling large numbers of bits.
Innovation Solution
The implementation of a binary in-memory adder organized in base-2n format using memory arrays for direct arithmetic computations, reducing data transportation frequencies and employing Perpetual Digital Perceptron (PDP) for compact and efficient storage and processing of arithmetic tables, allowing for scalable and efficient addition operations on arbitrary large numbers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional binary carry-chain adder is used, then addition operation can be performed, but power consumption increases significantly with increasing operational steps and data transportation frequencies
Solution Approach 1:
The patent merges the arithmetic operation and storage functions by implementing the adder directly within the memory array structure. The adder unit is integrated into the memory cell array, allowing arithmetic operations to be performed in-place without requiring separate ALU units and extensive data transportation through bus lines, thereby reducing power consumption while maintaining computing efficiency
Solution Approach 2:
The patent introduces a base-2n format as an intermediary representation between binary data and arithmetic operations. By organizing data in this specialized format within the memory array, the system enables direct arithmetic computation without conventional bit-level manipulations, reducing the number of operational steps and associated power consumption
2Productivity
If numerous bit-level manipulations are performed, then arithmetic operations can be completed, but bus-line congestions occur and computational efficiency decreases
Solution Approach 1:
The patent segments the arithmetic operation into a dedicated adder unit integrated within the memory array, separating the computation function from the data storage function. This segmentation allows arithmetic operations to be performed locally within the memory structure without requiring extensive data transportation through external bus lines, thereby reducing operational complexity and improving computing efficiency
Solution Approach 2:
The patent transitions from conventional linear bit-level manipulation to a multi-dimensional base-2n format organization within the memory array. This dimensional change enables parallel processing of arithmetic operations across multiple bits simultaneously, reducing the number of sequential operational steps and eliminating bus-line congestions
3Loss of energy
If base-2n format is used for arithmetic operations, then data transportation frequencies are reduced, but memory array size increases
Solution Approach 1:
The patent makes the memory array multi-functional by integrating both data storage and arithmetic computation capabilities within the same structure. The memory array serves dual purposes: storing data in base-2n format and performing arithmetic operations through the integrated adder unit, thereby avoiding the need for separate dedicated arithmetic logic units and minimizing overall system area
Data Source
AI summary
The base-2n in-memory adder device mainly comprises Perpetual Digital Perceptron (PDP) in-memory adder with Read Only Memory (ROM) arrays for storing the binary sum codes of the addition table for processing the addition operations of two n-bit binary integer operands. Since the integer numbers can be represented by the binary codes of multiple digits of base-2n integer numbers, the base-2n in-memory adder device can iterate multiple times of the digit-additions to complete the binary code addition for two m-digit base-2n integer operands. Consequently, the base-2n in-memory adder device can improve the computation efficiency and save the computation power by eliminating the data transportations between Arithmetic Logic Unit (ALU), registers, and memory units.