Digital Filter Approximate Adders for ISI Compensation

Solution Overview

Problem

As digital communication systems face increasing symbol rates and resulting inter-symbol interference (ISI), existing equalizers struggle to maintain performance while reducing power and area requirements, posing challenges for designers due to the need for increased complexity and faster processing.

Innovation Solution

The implementation of digital filters using a summation circuit with multiple partial product circuits and a carry-save adder (CSA) tree, which combines partial products into bits for two addends, with approximate adders used for least significant bits to simplify implementation and reduce power and area requirements, along with optional carry-propagate adders and truncation of least significant bits.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If traditional equalizers are used to combat ISI at higher symbol rates, then processing speed must increase, but power and area requirements increase significantly

Engineering Contradiction:

Improveprocessing speedVSAvoidpower consumption

Core Design Contradiction:

SpeedVSUse of energy by stationary object

Solution Approach 1:

The filter coefficients are divided into multiple segments, each processed by separate partial product circuits that operate in parallel. This segmentation allows the complex filtering operation to be broken down into smaller, more efficient units that can process data at higher speeds without requiring the entire filter to operate at full complexity, thereby reducing overall power consumption while maintaining processing speed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different portions of the filter output are processed with different levels of precision. The most significant bits use accurate adders while less significant bits use approximate adders. This local differentiation of quality allows the system to maintain high precision where needed for ISI compensation while using lower-power approximate operations where the precision requirement is relaxed, thus reducing overall power consumption.

Inventive Principle:

Principle #3Local quality

2Speed

If traditional equalizers are used to combat ISI at higher symbol rates, then processing speed must increase, but area requirements increase significantly

Engineering Contradiction:

Improveprocessing speedVSAvoidarea consumption

Core Design Contradiction:

SpeedVSArea of stationary object

Solution Approach 1:

The filter coefficients are divided into multiple segments, each processed by separate partial product circuits that operate in parallel. This segmentation allows the complex filtering operation to be broken down into smaller, more efficient units that can process data at higher speeds without requiring the entire filter to operate at full complexity, thereby reducing overall area consumption while maintaining processing speed.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different portions of the filter output are processed with different levels of precision. The most significant bits use accurate adders while less significant bits use approximate adders. This local differentiation of quality allows the system to maintain high precision where needed for ISI compensation while using lower-power approximate operations where the precision requirement is relaxed, thus reducing overall area consumption.

Inventive Principle:

Principle #3Local quality

3Use of energy by stationary object

If approximate adders are used in the CSA tree, then power and area requirements are reduced, but filtering accuracy decreases

Engineering Contradiction:

Improvepower consumptionVSAvoidfiltering accuracy

Core Design Contradiction:

Use of energy by stationary objectVSMeasurement precision

Solution Approach 1:

Different portions of the filter output are processed with different levels of precision. The most significant bits use accurate adders while less significant bits use approximate adders. This local differentiation of quality allows the system to maintain high precision where needed for ISI compensation while using lower-power approximate operations where the precision requirement is relaxed, thus reducing overall power consumption with minimal impact on filtering accuracy.

Inventive Principle:

Principle #3Local quality

Solution Approach 2:

The system performs filtering operations with slightly less than full precision for less significant bits, accepting the small accuracy loss in exchange for significant power and area savings. This partial action approach is justified because the human visual system and communication protocols can tolerate the small errors introduced by approximate adders in lower significance positions.

Inventive Principle:

Principle #16Partial or excessive action

Data Source

PatentUS11347476B2Digital filtering using combined approximate summation of partial products

Publication Date: 2022.05.31 CREDO TECHNOLOGY GROUP LTD

AI summary

Digital filters and filtering methods may employ truncation, internal rounding, and/or approximation in a summation circuit that combines multiple sets of bit products arranged by bit weight. One illustrative digital filter includes: a summation circuit coupled to multiple partial product circuits. Each partial product circuit is configured to combine bits of a filter coefficient with bits of a corresponding signal sample to produce a set of partial products. The summation circuit produces a filter output using a carry-save adder (“CSA”) tree that combines the partial products from the multiple partial product circuits into bits for two addends. The CSA tree has multiple lanes of adders, each lane being associated with a corresponding bit weight. The adders in one or more of the lanes associated with least significant bits of the filter output are approximate adders that trade accuracy for simpler implementation. In an illustrative receiver, the filter is coupled to a decision element that derives a sequence of symbol decisions.