Single Adder Stage for Floating Point Rounding
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Solution Overview
Problem
Current floating point datapath circuitry in programmable integrated circuit devices requires two stages of adders to compute the absolute value and round signed magnitude formatted numbers, leading to increased clock latency and area usage, as well as inefficiencies in handling sticky bits and unsigned numbers.
Innovation Solution
A single adder stage structure is introduced for floating point datapath circuitry within DSP blocks, combining the absolute value and rounding functions using look-up table circuitries to determine intermediate bits, thereby reducing the overall adder count and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If two stages of adders are used to compute absolute value and round signed magnitude formatted numbers, then calculation accuracy is improved, but clock latency and area usage increase
Solution Approach 1:
The patent combines the absolute value computation and rounding operations into a single adder stage by integrating the sticky bit generation and rounding logic within the same computational structure. This merging eliminates the need for sequential two-stage processing, achieving both accuracy and reduced latency simultaneously.
Solution Approach 2:
The single adder stage is designed to perform multiple functions: computing absolute value, generating sticky bits, and executing rounding operations all within one unified structure. This multi-functional design replaces what previously required separate dedicated circuits for each operation.
2Measurement precision
If two stages of adders are used to compute absolute value and round signed magnitude formatted numbers, then calculation accuracy is improved, but device area increases
Solution Approach 1:
The patent merges the absolute value computation and rounding circuits into a single integrated adder stage, eliminating redundant circuitry. By sharing common components such as the adder units and control logic between the two previously separate stages, the overall circuit area is reduced while maintaining computational accuracy.
Solution Approach 2:
The unified adder stage performs multiple functions including absolute value calculation, sticky bit generation, and rounding, replacing what previously required separate dedicated circuits. This multi-functional approach reduces the total component count and minimizes the overall device area.
3Ease of operation
If additional mantissa adder structure is included to support rounding, then rounding capability is improved, but clock latency and floating point adder area increase
Solution Approach 1:
The patent integrates the sticky bit generation and rounding logic directly within the existing adder stage structure, eliminating the need for separate additional mantissa adder structures. The same adder units that perform the primary addition also generate sticky bits and execute rounding operations.
Solution Approach 2:
The adder stage is designed as a universal structure that handles multiple operations: primary addition, sticky bit generation for rounding, and actual rounding execution. This multi-functional design eliminates the need for separate dedicated rounding circuits that would increase latency and area.
Data Source
AI summary
In accordance with some embodiments, a floating point number datapath circuitry, e.g., within an integrated circuit programmable logic device is provided. The datapath circuitry may be used for computing a rounded absolute value of a mantissa of a floating point number. The floating point datapath circuitry may have only a single adder stage for computing a rounded absolute value of a mantissa of the floating point number based on one or more bits of an unrounded mantissa of the floating point number. The unrounded and rounded mantissas may include a sign bit, a sticky bit, a round bit, and/or a least significant bit, and/or other bits. The unrounded mantissa may be in a format that includes negative numbers (e.g., 2's complement) and the rounded mantissa may be in a format that may include a portion of the floating point number represented as a positive number, (e.g., signed magnitude).