Redundant Floating-Point Representation for Parallel Arithmetic
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Solution Overview
Problem
Floating-point arithmetic is non-associative, leading to reproducibility issues and inefficiencies in parallel processing due to rounding and normalization during calculations, making it difficult to achieve consistent results when adding multiple values in a different order.
Innovation Solution
The introduction of the High-Precision Anchor (HPA) and Redundant High-Precision Anchor (RHPA) representations, which allow for fast, associative, and reproducible accumulation of floating-point numbers by using a programmable significance range and redundant bit representation, enabling parallelization without the need for extensive carry propagation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If floating-point arithmetic is used with rounding and normalization, then a finite number of bits can represent numeric values over a large range, but calculations become non-associative and difficult to parallelize
Solution Approach 1:
The patent segments floating-point numbers into multiple components (significand parts and exponent parts) that can be processed independently in parallel. By dividing the significand into high and low parts and handling exponent management separately, the system enables parallel computation paths while maintaining numerical accuracy through controlled rounding at specific stages.
Solution Approach 2:
The patent changes the parameters of floating-point representation by using alternative rounding modes and exponent handling strategies. It introduces different rounding behaviors (round-toward-zero, round-toward-positive-infinity, round-toward-negative-infinity) and exponent adjustment mechanisms that allow parallel operations to produce consistent results, effectively transforming the non-associative operation into an associative one.
2Reliability
If floating-point values are added sequentially to ensure reproducible results, then consistency is maintained, but the arithmetic becomes relatively slow
Solution Approach 1:
The patent performs preliminary actions by pre-calculating and storing rounding characteristics and exponent relationships before the main computation. It prepares multiple rounding results in advance and selects the appropriate one based on exponent comparisons, eliminating the need for sequential step-by-step rounding and enabling faster parallel execution while maintaining reproducibility.
Solution Approach 2:
The patent uses temporary intermediate representations and disposable computational paths that are discarded after use. It creates multiple candidate results through different rounding modes and selectively retains only the correct one, allowing parallel exploration of computation paths without the overhead of sequential verification, thus improving speed while ensuring reliability.
3Measurement precision
If carry propagation is performed extensively in traditional arithmetic, then accuracy is maintained, but the complexity and time required for calculations increases
Solution Approach 1:
The patent extracts the carry propagation operation from the main computation path and handles it separately through exponent-based control. By removing carries from intermediate significand additions and managing them through exponent comparisons and selective rounding, the system maintains accuracy without the complexity of extensive carry propagation through multiple stages.
Solution Approach 2:
The patent introduces exponent values and rounding mode selectors as intermediary elements that mediate between partial products and final results. These intermediaries control when and how carries are applied, replacing complex direct carry propagation with simpler controlled adjustments based on exponent relationships, thus reducing computational complexity while preserving accuracy.
Data Source
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AI summary
A method is provided for multiplying a first operand comprising at least two X-bit portions and a second operand comprising at least one Y-bit portion. At least two partial products are generated, each partial product comprising a product of a selected X-bit portion of the first operand and a selected Y-bit portion of the second operand. Each partial product is converted to a redundant representation in dependence on significance indicating information indicative of a significance of the partial product. In the redundant representation, the partial product is represented using a number of N-bit portions, and in a group of at least two adjacent N-bit portions, a number of overlap bits of a lower N-bit portion of the group have a same significance as some least significant bits of at least one upper N- bit portion of the group. The partial products are added while represented in the redundant representation.