Reconfigurable Neural Network Architecture for Embedded Systems

The patent merges the memory and processing units into a single integrated circuit chip. The synaptic coefficients are stored in memory blocks that are physically integrated with the processing units on the same chip, eliminating the need for external memory devices and reducing the number of inter-chip data exchanges, thereby significantly reducing power consumption while maintaining a compact form factor.

The patent segments the circuit into multiple specialized processing units (first processing unit for inference, second processing unit for training) with dedicated memory blocks. Each processing unit has its own associated memory block for storing synaptic coefficients, allowing parallel operation and reducing the need for data exchange between units, thus lowering overall power consumption.

The patent implements dynamic reconfiguration capability where the same memory blocks and processing units can be dynamically allocated to different computation phases (inference or training) based on runtime requirements. The control logic dynamically configures the data flow paths and memory access patterns, allowing efficient execution of both inference and training workloads without requiring separate dedicated hardware for each phase.

The patent designs universal processing units and memory blocks that can serve multiple functions. The first processing unit can handle both inference computations and gradient computations during training, while the second processing unit can handle training-specific operations. The memory blocks are universally accessible by both processing units, reducing the need for duplicate memory structures and simplifying the overall circuit architecture.